JPS58166757A - Formation of resistor - Google Patents

Formation of resistor

Info

Publication number
JPS58166757A
JPS58166757A JP57050740A JP5074082A JPS58166757A JP S58166757 A JPS58166757 A JP S58166757A JP 57050740 A JP57050740 A JP 57050740A JP 5074082 A JP5074082 A JP 5074082A JP S58166757 A JPS58166757 A JP S58166757A
Authority
JP
Japan
Prior art keywords
mask
regions
region
resistor
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57050740A
Other languages
Japanese (ja)
Inventor
Yuichi Suzuki
裕一 鈴木
Yoshio Watabe
由夫 渡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57050740A priority Critical patent/JPS58166757A/en
Publication of JPS58166757A publication Critical patent/JPS58166757A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/209Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of dispersion in the resistance value of the resistor to be formed even when discrepancy of positioning of a mask is generated by a method wherein between the high resistivity regions, the low resistivity region having width narrower than width of the regions thereof by the value in which discrepancy of mask positioning is estimated is formed. CONSTITUTION:A P<+> type diffusion treatment is performed to an N type epitaxial layer 2 on a substrate 1 through the mask 4 to form the regions 3, 3 to be the large resistivity regions. The mask 4 is removed by etching, and the mask 5 is applied thereon. The mask 5 thereof is narrower than width of the mask 4 by the previously decided value. The value thereof is so selected as to be larger than the value expected to be generated by positioning of the masks 4, 5. A diffusion treatment is performed through the mask thereof to make the region 6 to have smaller resistivity than the regions 3, 3, and moreover to be formed in the conductive type the same with the regions 3, 3, and the second impurity diffusion region is formed. The regions 3, 6, 3 are connected electrically, and the resistor 7 having the resistance value to be decided according to resistivities and geometrical sizes thereof is formed.

Description

【発明の詳細な説明】 (110発明0技衝分野 本発明は半導体基板に比抵抗の異なる抵抗領域から成る
抵抗を形成する際にそれら抵抗領域の配置及びその構造
を教養し比抵抗の形成方法に関する。
Detailed Description of the Invention (110 Invention 0 Technical field) The present invention provides a method for forming a resistivity by educating the arrangement and structure of resistive regions when forming a resistor consisting of resistive regions having different resistivities on a semiconductor substrate. Regarding.

(2)0発明の背景 従来、半導体基板に抵抗を形成する場合、抵抗の作シ易
さ、調整の容易性、抵抗の長さを所定長内に納めうろこ
と勢から比抵抗の異なる2種類又はそれ以上の抵抗領域
を組み合わせて所望の抵抗管形成する手段が用いられて
いる。これらの抵抗領域は同−一で形成されているが、
その抵抗領域の形成にマスクを用いていることから、そ
の位置合わせが必ずしも一致せず、抵抗値にバラツキが
生ずるのを避けることが出来ないという実情にある。
(2)0 Background of the Invention Conventionally, when forming a resistor on a semiconductor substrate, two types of resistors with different specific resistances are considered based on ease of fabrication, ease of adjustment, and keeping the length of the resistor within a predetermined length. A method is used to form a desired resistance tube by combining one or more resistance regions. These resistance regions are formed identically,
Since a mask is used to form the resistance region, the actual situation is that the alignment does not necessarily match, and it is impossible to avoid variations in resistance value.

(3)、従来技術と間聰点 即ち、従来の抵vc形成法では、比抵抗の相違の有無に
拘らず、夫々の抵抗領域は同一幅に形成されている一方
、抵抗用マスクの位置合わせに十分な整合をとシ得ない
のが現状であるから、上述抵抗領域は第1IIK示すよ
うに位置ずれして形成される。第111において、ai
bは第1のC形不純物拡散領斌、Cは第2のr形不純物
鉱散領域であや、ノWはずれ量を表わす。d。
(3) In the conventional technology and the gap point, that is, in the conventional resistor VC formation method, each resistor region is formed with the same width regardless of the presence or absence of a difference in specific resistance, while the resistor mask alignment At present, it is not possible to achieve sufficient matching, so the above-mentioned resistance regions are formed in a shifted position as shown in the first IIK. In the 111th, ai
b represents the first C-type impurity diffusion region, C represents the second r-type impurity mineralization region, and W represents the amount of deviation. d.

・はコンタクト廖である。第2図は第1図O1−N線矢
視断面図であシ、同一部分には同一の参照文字を付しで
ある。fは半導体基板、gはN形エピタキシャル層、h
は絶縁膜、tはアルミニウム電極である。
・is a contact liaison. FIG. 2 is a sectional view taken along the line O1-N in FIG. 1, and the same parts are given the same reference characters. f is a semiconductor substrate, g is an N-type epitaxial layer, h
is an insulating film, and t is an aluminum electrode.

上述のようなマスクの位置合わせずれが生ずすると、形
成された抵抗の抵抗値にバラツキが出てしまうのを避け
ることが出来ない。従って、抵抗の抵抗値tm度良く設
定出来ないという結果となシ、そのような精度が要求さ
れる部分には、上述O抵抗形成法の有する優れたAを活
用し得す、その方法によってはその抵抗を形成し得ない
ことKなる。
If the mask misalignment as described above occurs, it is impossible to avoid variations in the resistance values of the formed resistors. Therefore, the result is that the resistance value tm of the resistor cannot be set accurately.However, in parts where such precision is required, the excellent A of the above-mentioned O resistor formation method can be utilized, depending on the method. It becomes impossible to form that resistance.

(4)0発明の目的 本発明は上述したような従来の抵抗形成法の有する欠点
#C鑑みて創案されたもので、その目的はマスクずれが
生じても形成される抵抗の抵抗値にバラツキが生じない
抵抗の形成方法を提供することにある。
(4) 0 Purpose of the Invention The present invention was devised in view of the drawback #C of the conventional resistor forming method as described above, and its purpose is to eliminate variations in the resistance value of the resistor formed even if mask displacement occurs. The object of the present invention is to provide a method for forming a resistance that does not cause the occurrence of resistance.

(5)0発明の構成 そして、この目的は一導電形の半導体基板に形成せんと
する抵抗の両端部に反対導電形の第1の抵抗領域とこれ
ら第1の抵抗領域間に介在する反対導電形の第20抵抗
領域を有する抵抗を形成するに際し、上記第1の抵抗領
域を上記第2の抵抗領域の幅よ)11I!広く形成し、
上記第2の抵抗領域を第1の不純物拡散領域よシも比抵
抗が小さく且つ上記第1の不純物拡散領域の両端部に重
なる第2の不純物拡散領域として形成することによって
達成される。
(5) Structure of the Invention The purpose of this invention is to provide a first resistance region of an opposite conductivity type at both ends of a resistor to be formed on a semiconductor substrate of one conductivity type, and an opposite conductivity region interposed between these first resistance regions. When forming a resistor having a 20th resistance region of the shape, the width of the first resistance region is the width of the second resistance region) 11I! Form widely,
This is achieved by forming the second resistance region as a second impurity diffusion region that has a smaller resistivity than the first impurity diffusion region and overlaps both ends of the first impurity diffusion region.

(6)1発明の実施例 以下、添付図面を参照しながら、本発明の詳細な説明す
る。
(6) First Embodiment The present invention will be described in detail below with reference to the accompanying drawings.

先ず、第3図に示すように半導体基I[1上KN形工ピ
タキシヤル層2を形成する。
First, as shown in FIG. 3, a KN-shaped pitaxial layer 2 is formed on the semiconductor substrate I [1].

次いで、この基板1ON形工ピタキシヤル層2に1第4
図に示すように、高比抵抗を有する第1の不純物拡散領
域3.3t−拡散形成するためのマスク4を施し、この
マスクを介して領域3.3を比抵抗の大きい領域化すべ
くP情に拡散処理を施す。
Next, on this substrate 1ON formed pitaxial layer 2, a fourth layer is applied.
As shown in the figure, a mask 4 for forming the first impurity diffusion region 3.3t-diffusion having a high specific resistance is applied, and P information is applied to make the region 3.3 a region with a high specific resistance through this mask. Apply diffusion treatment to

その徒に、マスク4を蝕刻し去シ、その上に第5図に示
すように、マスク5を施す。このマスク5は第7図に示
すように1マスク4の幅よシ予め決められた値だけ狭い
。この値はマスク4.5の位置合わせで生ずるであろう
位首合わせずれ量よ〕大きく選ばれる。このマスクを介
して第5図の点線で囲まれる領域6を上記領域3.3よ
シ比抵抗小さく且つ領域3,3と同一導電形に拡散処理
を施して第2の不純物拡散領域とする。従って、第2の
不純物拡散領域6の両端は第1の不純物拡散領域3.3
の一端と重なシ合っている。これら領[3、6、3t′
i電気的に結合されており、それら比抵抗及び幾何学的
寸法によって決まる抵抗値含有する抵抗7となシうる。
Then, the mask 4 is etched and removed, and a mask 5 is applied thereon as shown in FIG. As shown in FIG. 7, this mask 5 is narrower than the width of one mask 4 by a predetermined value. This value is chosen to be larger than the amount of misregistration that would occur in the alignment of mask 4.5. Through this mask, a region 6 surrounded by a dotted line in FIG. 5 is diffused to have a lower specific resistance than the region 3.3 and the same conductivity type as the regions 3, 3, thereby forming a second impurity diffusion region. Therefore, both ends of the second impurity diffusion region 6 are connected to the first impurity diffusion region 3.3.
It overlaps one end of the . These territories [3, 6, 3t'
i is electrically coupled and can be a resistor 7 with a resistance value determined by their resistivity and geometrical dimensions.

この処理の終了後、マスク5を蝕刻し去り、第6図に示
すように、高比抵抗の領域3,3のうちの1領域6と重
ならない所望位置にコンタクト窓8を有する電気的絶縁
被膜9が上記領域3.6.3上に被覆され、そのコンタ
クト窓8にアルミニウム電極10を形成する。このアル
ミニウム電極10は高比抵抗つtn低抵抗である領域3
.3との間に嵐好なオー2ツタコンタクト管生じさせ得
る。
After this process is completed, the mask 5 is etched away, and as shown in FIG. 9 is coated on said area 3.6.3 forming an aluminum electrode 10 in its contact window 8. This aluminum electrode 10 has a region 3 with high specific resistance and low tn resistance.
.. A smooth contact tube can be created between the two.

そして、電極9.9間の抵抗7は半導体基板l上に形成
される各種機能回路のうちの所定の回路に接続されてそ
こに組み入れられる。
The resistor 7 between the electrodes 9 and 9 is connected to and incorporated into a predetermined circuit out of various functional circuits formed on the semiconductor substrate l.

この本発明方法で形成される抵抗はその第1の不純物拡
散領域3,3の幅が第20不純物拡散領域6の幅より広
くされているから、たとえマスクの位置合わせにずれが
生じても1抵抗7の抵抗値にバラツキを生ぜしめてしま
う虞れはなくなる。従って、精度の良い抵抗を形成しう
る。この効果は異なる比抵抗を有する不純物領域から抵
抗を作る場合に得られる利点即ち、作り易さ、−整の容
易性*1失うことなく得られる。又、領域3.3を低抵
抗に形成しているから、アル(=ウム電極lOとの間の
電気的接続性が良好になる。
In the resistor formed by the method of the present invention, the width of the first impurity diffusion regions 3, 3 is made wider than the width of the 20th impurity diffusion region 6, so even if a misalignment of the mask occurs, There is no possibility that the resistance value of the resistor 7 will vary. Therefore, a highly accurate resistor can be formed. This effect can be obtained without losing the advantages obtained when resistors are made from impurity regions having different specific resistances, that is, ease of production and ease of adjustment *1. Furthermore, since the region 3.3 is formed to have a low resistance, the electrical connectivity with the aluminum electrode IO is improved.

上記実施例で鉱、高比抵抗領域3.3を低比抵抗領域6
より先に形成しているが、逆にしてもよい。
In the above example, the high resistivity region 3.3 and the low resistivity region 6
Although they are formed first, they may be formed in the opposite direction.

(7)0発明O効果 以上費するに、本発明によ多形成される抵抗はその両端
に高比抵抗領域を形成し、これら高比抵抗領域間に高比
抵抗領域の幅よシ!スク位置合わせずれを見込んだ値だ
け狭い幅の低比抵抗領域を形成しているから、抵抗の形
成に際してマスクの位置合わせずれが生じたとしても、
形成されえ抵抗にバラツキを生じさせることはない。こ
の効果は異なる比抵抗を用いて抵抗を作る場合に得られ
る利点を失うことなく享受田来る。又、上記効果と同時
に、電極とのコンタクト柱管向上させ得ている。
(7) 0 Effects of the Invention In other words, the multi-layered resistor of the present invention forms high resistivity regions at both ends, and the width of the high resistivity region is the same as that between these high resistivity regions. Since a low resistivity region is formed with a width that is narrow enough to account for misalignment of the mask, even if misalignment of the mask occurs when forming the resistor,
However, it does not cause variations in resistance. This effect comes without losing the advantages obtained when creating resistors using different resistivities. Moreover, at the same time as the above effect, the contact column with the electrode can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

絡1図及び第2図は従来の方法で形成される抵抗の平面
図及び縦断面図、第3図乃至第6図は本□ 発明の各工程を示す図、第7図は本発明で用いる各マス
クの幾何学的大きさ、従って形成される抵抗の各領斌O
大きさを図解する図である。 図において、1は半導体基板、3.3は第1の不純物拡
散領域、6は第2の不純物拡散領域である。 特許出願人 富士通株式全社 第1図 第2図 第3図 第4図 第5図
Figures 1 and 2 are a plan view and a vertical cross-sectional view of a resistor formed by a conventional method, Figures 3 to 6 are diagrams showing each step of the present invention, and Figure 7 is a diagram showing the steps of the present invention. The geometric size of each mask, and therefore each region of the resistor formed
It is a diagram illustrating the size. In the figure, 1 is a semiconductor substrate, 3.3 is a first impurity diffusion region, and 6 is a second impurity diffusion region. Patent applicant Fujitsu Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 一導電形の半導体基板に形成せんとする抵抗の両端IS
K反対反対導電箔1の抵抗領域と鉄鉱1の抵抗領域間に
介在する反対導電形の第2の抵抗領域を有する抵抗を形
成するに際し、上記第1の抵抗領域を上記第2の抵抗領
域の幅より幅広く形成し、上記第2の抵抗領域を該第1
の不純物拡散領域よシも比抵抗が小さく且つ上記第1の
不純物拡散領域の両端部に重なる第2の不純物拡散領域
として形成することを特徴とする抵抗の形成方法。
Both ends IS of a resistor to be formed on a semiconductor substrate of one conductivity type
When forming a resistor having a second resistance region of the opposite conductivity type interposed between the resistance region of the K-opposite conductive foil 1 and the resistance region of the iron ore 1, the first resistance region is replaced with the second resistance region of the iron ore 1. The second resistance region is formed wider than the first resistance region.
A method for forming a resistor, characterized in that the impurity diffusion region is formed as a second impurity diffusion region having a small resistivity and overlapping both ends of the first impurity diffusion region.
JP57050740A 1982-03-29 1982-03-29 Formation of resistor Pending JPS58166757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57050740A JPS58166757A (en) 1982-03-29 1982-03-29 Formation of resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57050740A JPS58166757A (en) 1982-03-29 1982-03-29 Formation of resistor

Publications (1)

Publication Number Publication Date
JPS58166757A true JPS58166757A (en) 1983-10-01

Family

ID=12867231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57050740A Pending JPS58166757A (en) 1982-03-29 1982-03-29 Formation of resistor

Country Status (1)

Country Link
JP (1) JPS58166757A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288355A (en) * 1985-10-15 1987-04-22 Nec Corp Resistor for IC
JPS63271965A (en) * 1987-04-28 1988-11-09 Nec Corp Resistance of compound semiconductor substrate
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50148071A (en) * 1974-05-20 1975-11-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50148071A (en) * 1974-05-20 1975-11-27

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor
JPS6288355A (en) * 1985-10-15 1987-04-22 Nec Corp Resistor for IC
JPS63271965A (en) * 1987-04-28 1988-11-09 Nec Corp Resistance of compound semiconductor substrate

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