JPS58182A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To obtain an isolating region with a smooth surface free of crystal defects by a method wherein the isolating region is constituted of a two layer structure consisting of a polycrystalline semiconductor region and an insulator region, in a process for the establishment of an element isolating region on a monocrystalline substrate constituting a MOS type semiconductor device. CONSTITUTION:A P type or N type Si substrate 1 is coated with an Si3N4 film 2 and an opening is provided at a place corresponding to the element isolating region. A groove is formed in the substrate 1 exposed in the opening by the anistropic or ion etching method. Next, the entire surface including the groove is coated with a polycrystalline Si layer 3 by the CVD method. The layer 3 in the groove is not in contact with the layer 3 on the film 2. Elements separating field ions are then implanted. By using the CVD method, an SiO2 film 5 is grown, again the part in the groove not in contact with the other part. The heat generated in this CVD process causes the layer 3 within the groove to diffuse ions to the surrounding groove wall for the formation of a diffused layer 6. Next, the entire surface is covered with a resist film 7, which is followed by a reactive ion etching process wherein the film 5 is removed together with the film 7. Further, the layer 3 and the film 2 on the substrate surface are removed, with the portions of the film 5 and the layer 3 in the groove only surviving the dismantling process.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 type semiconductor device. 2. Description of the Related Art Conventional MOS semiconductor devices have generally been constructed by forming isolation regions between elements by selective oxidation of a substrate. However, when constructing a semiconductor device by selective oxidation of a substrate, there are drawbacks such as limitations on the size of the semiconductor device, zero level difference on the surface of the semiconductor device, and crystal defects in the semiconductor device.The present invention overcomes the drawbacks of the prior art. In order to achieve the Supporting, reduction of crystal defects,
The object of the present invention is to provide a Mol semiconductor in which parasitic capacitance is controlled and wrinkles are further reduced.Examples will be described in detail below using examples.

Figure 1 shows the conventional technology, MO1! ! This figure shows the cross-section of an element isolation region, which is the simplest structure of a conductor device, as an example, and a SiC oxide film 2 is formed by thermal oxidation using silicon nitride [1] as a mask. . The region 3 is an element isolation field ion implantation region. In this case, the fact that the oxide film goes under the silicon nitride film and that the ion implantation in the isolation field spreads widely in the lateral direction prevents the semiconductor device from becoming smaller. By thermally oxidizing a t-shaped substrate to a thick thickness, crystal defects and steps on the semiconductor surface occur. #! Figure 2 shows an example of the present invention in which a polycrystalline silicon layer and a silicon oxide insulating film layer are doubly buried in the element isolation region of a silicon substrate. Cross-sectional view of the field (-) and its manufacturing process sequence (α) to (-
). In (a), grooves are formed by partially anisotropically etching or ion etching a Pal silicon substrate 1. In FIG. In (b), polycrystalline silicon S is deposited using the OVD method, and field ion implantation is performed for isolation between elements. In (C), an oxide film 4 is deposited on the entire surface using the OVD method, and silicon nitride is used as a mask on the silicon substrate surface.
is formed. The region 5 is a dense square or Piml diffusion region in which element isolation field ions are diffused into the silicon substrate. The diffusion coefficient in the silicon substrate is smaller than that in polycrystalline silicon, and because the diffusion in the depth direction of polycrystalline silicon is fast, the lateral spread of the high concentration or P:lIL diffused silicon in region 5 can be controlled to be small. can. In (d), an RMAH resist is formed on the entire surface by spin coding. For (-), reactive ion etching results in a steeper etching rate.
Remove the resist and OVN oxide film at the same time, leaving the σVD oxide film only in the recesses of the silicon substrate. Next, remove the polycrystalline silicon layer and silicon nitride layer on the surface, and remove the polycrystalline silicon layer and silicon nitride layer on the silicon substrate. A MOall semiconductor device is obtained in which a crystalline silicon layer and an OVD oxide film layer are doubly buried.

(-) is a plan view of the element isolation field 0IFr of the Mol type semiconductor device according to the present invention. According to the present invention, the lateral spread of element isolation field ion implantation can be controlled to be small,
Since the patterning accuracy is determined by the ion etching accuracy, the Mol type semiconductor device can be further miniaturized. The size of the parasitic capacitance can be controlled by the OVD oxide film thickness. Further, by doubling polycrystalline silicon and own-B silicon into the element isolation region, a semiconductor device is provided that does not generate steps or crystal defects on the surface of the semiconductor substrate.

[Brief explanation of the drawing]

#! Figure 1: Cross-sectional view of conventional O element field 1
---Silicon nitride film 2 ---Silicon oxide 3 ---Element isolation ion implantation region 4 ---
Semiconductor substrate FIGS. 2(a) to 2(#) are a sectional view of an isolation field between elements of a MOg semiconductor device according to the present invention and a sequential diagram of its manufacturing process. 1... Silicon substrate 2... Silicon nitride film 3... Polycrystalline silicon 4... Element isolation field ion implantation 5...
...-OV D silicon oxide film 6... Diffused silicon substrate 7...-II
M A M Registration and above Applicant Josha Eiwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami Figure 1 1! : −' ”j to float he1 υ

Claims (2)

[Claims] (1) An MO characterized in that a single crystal semiconductor substrate is doubly embedded with a polycrystalline semiconductor region and an insulating film region.
B-manufactured semiconductor device. (2) MO8I! according to claim 1, characterized in that a polycrystalline semiconductor region and an insulating film region are placed in double layers in the element isolation region of the single crystal semiconductor substrate.
Semiconductor equipment.