JPS5818921A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5818921A JPS5818921A JP56117435A JP11743581A JPS5818921A JP S5818921 A JPS5818921 A JP S5818921A JP 56117435 A JP56117435 A JP 56117435A JP 11743581 A JP11743581 A JP 11743581A JP S5818921 A JPS5818921 A JP S5818921A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- oxide film
- semiconductor substrate
- leakage current
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、半導体装置の製造方法では、半導体基板の所定領
域に所望の素子を構成するための不純物領域を形成し死
後、これに炉内で熱処理を施して所望の仕様を満す半導
体装置を製造している。しかしながら、このような半導
体装置の製造方法では、熱処理の際に炉内の汚れや半導
体基板の表面に付着した不純物が飛散し、半導体基板表
面の領域が汚染される。その結果、リーク電流が増大し
て素子特性を劣化する問題があり九。Conventionally, in the manufacturing method of a semiconductor device, an impurity region for forming a desired element is formed in a predetermined region of a semiconductor substrate, and after death, the impurity region is heat-treated in a furnace to manufacture a semiconductor device that meets desired specifications. ing. However, in such a semiconductor device manufacturing method, dirt in the furnace and impurities attached to the surface of the semiconductor substrate are scattered during heat treatment, and the surface area of the semiconductor substrate is contaminated. As a result, there is a problem that leakage current increases and device characteristics deteriorate.
本発明は、かかる点に鑑みてなされたもので、リーク電
流の発生を防止して素子特性を向上させる仁とができる
半導体装置の製造方法を見出したものである。The present invention has been made in view of this problem, and is the result of the discovery of a method for manufacturing a semiconductor device that can prevent the occurrence of leakage current and improve device characteristics.
以下、本発明Ｏ実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図に示す如く、例えば不純物浸度が６ Ｘ １０
” ｉ’ Ｏ半導体基板１０所定領域にｐ導電型の不純
物拡散を施し、拡散深さが約５声ｍの不純物領域２，１
を約３０ Ａｍの間隔で形成する。次いで、半導体基板
１及び不純物領域２゜３の露出表面に、１００℃以下の
雰囲気中で低温酸化膜を形成した後、例えば１１００℃
のスチーム雰囲気で３０分間熱処理を施す。As shown in Fig. 1, for example, the degree of impurity penetration is 6 x 10
"i' O A predetermined region of the semiconductor substrate 10 is doped with p-conductivity type impurity to form impurity regions 2 and 1 with a diffusion depth of about 5 m.
are formed at intervals of about 30 Am. Next, a low-temperature oxide film is formed on the exposed surfaces of the semiconductor substrate 1 and the impurity region 2°3 in an atmosphere of 100°C or lower, and then heated to a temperature of 1100°C, for example.
Heat treatment is performed in a steam atmosphere for 30 minutes.
ζこで、低温酸化膜の形成方法としては、純水を１００
ｃに加熱して得た水蒸気を半導体基板の露出表面に接触
せしめて形成するもの中１００℃以下の低温の雰囲気中
で形成すゐものなどでも良い。ζHere, as a method for forming a low-temperature oxide film, pure water is
Among those formed by contacting the exposed surface of the semiconductor substrate with water vapor obtained by heating to a temperature of 100.degree. C., it may also be formed in an atmosphere at a low temperature of 100.degree. C. or lower.
然る後、前述の熱処理によって形成された酸化膜を濃酸
で除去し、不純物領域１８３関０１７−り電流を低温酸
化膜の形成処理時間ごとに調べたところ、第２図に示す
如き結果を得九、同図から明らかな如く、３０分以上の
処理時間をかけて低温酸化膜を形成した後に熱処理を施
したものでは、リーク電流はＩＩＡＡ以下になっておシ
極めて優れた素子特性を有することが判る。Thereafter, the oxide film formed by the above-mentioned heat treatment was removed with concentrated acid, and the current flowing through the impurity region 183 was examined for each time period of the low-temperature oxide film formation process.The results shown in FIG. 2 were obtained. As is clear from the figure, in the case where a low-temperature oxide film was formed over a processing time of 30 minutes or more and then heat-treated, the leakage current was less than IIAA, and the device had extremely excellent device characteristics. I understand that.
以上説明した如く、本発明に係る半導体装置の製造方法
によれば、所定領域の表面に低温酸化膜を形成した彼に
熱処理を施すようＫしたので、リーク電流の発生を防止
して素子特性の向上を図った半導体装置を容易に製造で
きるものである。As explained above, according to the method for manufacturing a semiconductor device according to the present invention, since a low-temperature oxide film is formed on the surface of a predetermined region and then heat treatment is performed, the generation of leakage current is prevented and the device characteristics are improved. It is possible to easily manufacture an improved semiconductor device.
第１図は、本発明方法によシ製造された半導体装置の断
面図、第２図は、低温酸化ＭＯ形成時間とリーク電流の
関係を示す特性図である。
１・・・半導体基板、２．３・−不純物領域。FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method of the present invention, and FIG. 2 is a characteristic diagram showing the relationship between low-temperature oxidized MO formation time and leakage current. 1...Semiconductor substrate, 2.3--impurity region.
Claims (1)
型の不純物領域を形成する工程と、前記半導体基板の所
定＠斌に低温酸化膜を形成した後熱処理を施す１鶏とを
具備することを特徴とする半導体装置の製造方法。The present invention comprises a step of forming an impurity region of a predetermined conductivity type constituting a desired element on a semiconductor substrate of one conductivity type, and a step of performing heat treatment after forming a low temperature oxide film in a predetermined area of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117435A JPS5818921A (en) | 1981-07-27 | 1981-07-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117435A JPS5818921A (en) | 1981-07-27 | 1981-07-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5818921A true JPS5818921A (en) | 1983-02-03 |
Family
ID=14711571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56117435A Pending JPS5818921A (en) | 1981-07-27 | 1981-07-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818921A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59108068A (en) * | 1982-12-11 | 1984-06-22 | Nitto Electric Ind Co Ltd | Paste composition |
-
1981
- 1981-07-27 JP JP56117435A patent/JPS5818921A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59108068A (en) * | 1982-12-11 | 1984-06-22 | Nitto Electric Ind Co Ltd | Paste composition |
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