JPS5820044A - Staff synchronizing system - Google Patents

Abstract

PURPOSE:To decrease the pull-in time of a voltage controlled oscilator when the shift of the transmission input signal frequency is restored, by inhibiting writing into a phase comparator when the all-staff or all-nonstaff is detected at the receiving side. CONSTITUTION:In case the frequency of the transmission input signal is considerably shifted for a digital multiplex converter of staff synchronizing system, the all-staf or all-nonstaff state is obtained at the transmitting side. This state signal is detected at the receiving side by an all-staff/all-nonstaff detecting circuit 25 and via a destaff control circuit 19. Then an inhibiting signal is transmitted to inhibit the writing clock WCLK given from the circuit 19 and supplied to a phase comparator 26 of a phase locking circuit 23. Thus the reading clock RCLK is delivered from the circuit 26 to lock a voltage control oscillator 29 to the center frequency. When the transmission input signal frequency is restored to the original state, the circuit 25 stops function and the clock WCLK is supplied to the circuit 26 from the circuit 19. Thus the oscillator 29 pull-in the WCLK immediately and is restored to the normal state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stuff synchronization method for a stuff synchronization digital multiplex converter, which speeds up the pull-in time of a voltage controlled oscillator when the input signal frequency shifts significantly and returns again.

When multiplexing multiple asynchronous digital signals and transmitting them as a single signal with a high frequency, the block diagram of a conversion device is generally shown. (5) shows the transmitting part and (b) shows the receiving part. There is.

In the figure, 1 and 2 are transmission channel sections, 3.14 is a bipolar/unipolar conversion section (hereinafter referred to as B/U C0NV),
4 and 22 are Pat7 memory, 5.15 is a tie extractor, 6 is a phase comparator, 7 is a multiplexing section, 8 is a stuff control circuit (justification control circuit), and 9 is a multiplexer. 10 is a main oscillator, 11 is a transmitting side clock generation circuit, 12.24 is an Any2 bipolar conversion unit (hereinafter referred to as U/BCONV), and 16 is a four clock generation circuit on the receiving side.

17 is a frame synchronization circuit, 18 is a separation unit, 19 is a destuffing control circuit, 20.21 is a reception channel unit, 2
3 is a phase locked circuit.

The operation is as follows: The input low-order group signal of 8IN (Iborts code) is converted into Unibord 2 code by B/U C0NV3, and this signal is extracted by the timing extractor 6. ] (Write to the rough memory 4. On the other hand, a synchronization signal frequency that is slightly higher than the input low-order group frequency from the transmitting side clock generator 11 is input to the stuff control circuit 8, and the pulses generated thereby are input to the stuff control circuit 8. Gino (
By inserting four pulses of memory 7a, the frequency deviation of multiplexing in the multiplexer 9 is absorbed. At this time, information as to whether or not a stuff pulse is inserted is separately superimposed on the multiplexed signal as a stuff designation pulse. Further, frame pulses and various service pulses for synchronization on the receiving side are also superimposed on the multiplexed signal. The multiplexed signals sent from each transmission channel section 1゜2, etc. are multiplexed by the multiplexing section 9 L, U/B C0NV12K"
CA4yN-') code and sends it to reception@. On the receiving side, the B/UCONV 14 converts the signal into a Schnibolla code, and the timing pulse extracted by the timing extraction circuit 15 operates the receiving side black V error generation circuit 16, and the frame synchronization circuit 17 receives the transmitted signal. The signal is synchronized and separated into each channel by the separation section 1B. On the other hand, the stuff designation pulse is detected and the stuff pulse is separated from the signal. After being separated into each channel by the separation unit 18, they are written into the buffer memory 22, but the write clock is prohibited by the destuff control circuit 19 where stuff pulses, stuff designation pulses, and frame pulses are inserted. I am doing a lot of removal.

A good signal written to the buffer memory 22 is sent to the phase synchronization circuit 2.
Smoothed by the voltage controlled oscillator in 3, the signal is read out as the original signal of the lower order group by the 4-way read-out function U/
B Converted to cipolar code by C0NV24 and R
Sent from OUT. At this time, the write lock and the read t1 lock are compared by a phase comparator circuit in the phase synchronization circuit 23, and the read clock is made to follow the frequency of the input low-order group signal on the transmitting side. However, if the frequency of the input low-order group signal that is input as small as 8IN on the transmitting side is significantly shifted for some reason, all the places where stuffing pulses can be inserted will be in an all-stuffed state or an all-unstuffed state.
On the receiving side, the pull-in range of the voltage controlled oscillator of the phase synchronization circuit 23 is out of range, resulting in a state of □. In this state, even if the input low-order group signal from 8IN on the transmitting side returns to its normal frequency, it takes time for the voltage controlled oscillator to pull in, so the disadvantage is that it takes time for the output signal from ROUT to return to normal. There is.

An object of the present invention is to provide a stuff synchronization method that speeds up the pull-in time of a voltage controlled oscillator when the input low-order group signal frequency is significantly shifted and then restored again.
Ru.

In order to achieve the above object, the present invention prohibits write locking of the phase comparison circuit of the phase synchronization circuit when all stuff or all non-stuff is detected on the receiving side in a digital multiplex converter using a stuff synchronization method. By doing this, the phase comparator circuit outputs the read clock, the voltage controlled oscillator is locked to the center frequency, and when the input low-order group signal frequency to the transmitting side returns, the voltage controlled oscillator is quickly pulled in. It is characterized by being possible.

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a block diagram of a stuffing type digital multiplex converter according to an embodiment of the present invention, where ^ is a transmitting section, (b) is a receiving section, and FIG. 3 is a block diagram of a known phase synchronization circuit.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols.

25 is an all-stuff, all-nonstuff detection circuit;
26 is a phase comparator circuit, 27 is a low-frequency r wave generator, and 28 is an amplification i.
, 2o is a voltage controlled oscillator.

The only difference in FIG. 2 from FIG. 1 is that a separating section IBK all-stuff and all-nonstuff detection circuit 25 of the receiving section shown in FIG. 2 is provided. Therefore, normal operation is the same as described above. If the frequency of the input low-order group signal other than 8 IN of the transmitting section is significantly shifted for some reason, all the places where over-sister 7 pulses can be inserted as described above become all stuffed state or all non-stuffed state. Jin's state O
By passing the signal through the destuff control circuit 19 on the receiving side, the di-all stuff and all-non-stuff detection circuit 25
The destuff control circuit 19 detects the error, sends an inhibit signal, and inputs the input to the phase comparison circuit 26 in FIG. 3. 2'y (in Figure 3, WCLI() is prohibited.In addition to this, the phase comparator circuit 26 in Figure 3 is read out (RCLK in Figure 3) is one of the
1 output and the voltage controlled oscillator 29 is locked to the center frequency.

If the frequency of the input low-order group signal of the transmitter 8IN returns to its original state, it will be in a normal state, so all staff
The all non-metallic detection circuit 25 does not operate, the inhibition of the writing clock from the desktop control circuit 19 and the like is lifted, and writing is input to the phase comparator circuit 26 without any interference. However, since the voltage controlled oscillator 29 operates at a center frequency that is almost the same as the write lock, it immediately pulls in the write lock, follows the input low-order group frequency on the transmitting side, and immediately returns to the normal state.

As explained in detail above, according to the present invention, if the input low-order group signal frequency on the transmitting side deviates significantly for some reason and returns to normal, it can be immediately restored to normal and the time required for communication to be interrupted can be greatly reduced. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional stuffing type digital multiplex conversion device, FIG. 2 is a block diagram of a stuffing type digital multiplexing scissors according to an embodiment of the present invention, and FIG. 3 is a phase synchronization circuit. 1.2 is the transmission channel section, 3.14 is the B/U C
0NV, 4.22 is Py7y/49,5. 15 is a timing extractor, 6 is a phase comparator, 7 is a multiplexing section, $ is a stuff control circuit, 9 is a multiplexing section, 10 is a main oscillator, 11 is a transmission side clock generation circuit, is a separation section, 19
is a destuff control circuit, 20° 21 is a reception channel section, 23 is a phase synchronization circuit, 25 is an all-stuff and all-nonstuff detection circuit, 26 is a phase comparison circuit, 2) is a low-frequency P wave generator, 28 is an amplifier, 29 is a voltage controlled oscillator. 1 (f3) Contradictory diagram

Claims (1)

[Claims] A stuff synchronization method, in a digital multiplex converter using a stuff synchronization method, characterized in that when all stuff or all non-stuff is detected on the receiving side, writing clocks to the phase comparison circuit of the receiving side phase synchronization circuit is prohibited.