JPS58200565A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58200565A JPS58200565A JP57083099A JP8309982A JPS58200565A JP S58200565 A JPS58200565 A JP S58200565A JP 57083099 A JP57083099 A JP 57083099A JP 8309982 A JP8309982 A JP 8309982A JP S58200565 A JPS58200565 A JP S58200565A
- Authority
- JP
- Japan
- Prior art keywords
- type layer
- layer
- input terminal
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置（以下ＩＣと称する）の静
電破壊防止技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for preventing electrostatic damage in semiconductor integrated circuit devices (hereinafter referred to as IC).
バイポーラ・リニア■ＣＫ、おいては通常回路の入力端
子にベース拡散層が使われており、基体表面の導電型が
Ｎ型である場合ベースはＰ型の拡散層により形成される
が、このベースへの＾圧靜電気の印加によるＩＣの静電
破壊が問題となっている。通常、 ＰａＩベースはＢ（
ボロン不純物）の拡散によ゛ってＮ１１基体表面より２
〜３μｍの深さの浅いＰＮ接合ができるよ５ｖ−形成さ
れるが、この上ＫＡＪ（アルミニウム）電極をコンタク
トさせる場合、浅い拡散層ｔはＡＪ−Ｓｉ合金現象の進
行により耐破壊強度がよりくなり、４１にコンタクト孔
の角部直下におい【静電破壊を容易におこすおそれがあ
る。In bipolar/linear CK, a base diffusion layer is usually used for the input terminal of the circuit, and if the conductivity type of the substrate surface is N type, the base is formed by a P type diffusion layer, but this base Electrostatic damage to ICs due to the application of high pressure electricity to ICs has become a problem. Usually, the PaI base is B(
2 from the surface of the N11 substrate due to the diffusion of boron impurities).
5V- is formed so that a shallow PN junction with a depth of ~3 μm is formed, but when contacting with a KAJ (aluminum) electrode, the shallow diffusion layer t has a higher breakdown strength due to the progress of the AJ-Si alloy phenomenon. 41, there is a risk of electrostatic damage occurring directly under the corner of the contact hole.
このようなＩＣの静電破壊を防止するための対策とし”
（（１）第１図に示すように基板ｌ上で外部導出用端子
（パッド）２とＩＣの入力端子３との間Ｋ例えば保繰ダ
イオードのような静電破壊防止素子（ダイオード）４を
挿入する、（２）第２図に示すように外部導出用端子２
とＩＣとの間の配線５の距離を増長化する、（３１入力
端子に抵抗コンタクト部を入れる勢によりＰ型層７のコ
ンタクト部の面積を大きくする等が考えられる。Measures are taken to prevent such electrostatic damage to ICs.
((1) As shown in Figure 1, an electrostatic breakdown prevention element (diode) 4 such as a protection diode is connected between the external lead-out terminal (pad) 2 and the input terminal 3 of the IC on the substrate l. (2) Insert the external lead terminal 2 as shown in Figure 2.
It is conceivable to increase the distance of the wiring 5 between the input terminal 31 and the IC, or to increase the area of the contact portion of the P-type layer 7 by inserting a resistive contact portion into the input terminal 31.
しかしこれらの対策は静電破壊防止を有効ならしめよう
とするといずれも基体表面で広い面積をとることになり
、半導体チップ面積の大形化は避けられないととくなっ
た。However, if these measures are to be effective in preventing electrostatic discharge damage, they all require a large area on the substrate surface, making it inevitable to increase the area of the semiconductor chip.
本＠明は上記した問題を解決するため艮なされたもので
あり、その目的とするところはチップ面積を大形化する
ことなく■ＣＫおける静電破壊防止レベルを向上するこ
とＫある。The present invention was designed to solve the above-mentioned problems, and its purpose is to improve the level of prevention of electrostatic damage in CK without increasing the chip area.
第４図は本発明による一実施例を示し、第５図は第４図
におけるＡ−Ａ’断面を示すものである。FIG. 4 shows an embodiment according to the present invention, and FIG. 5 shows a cross section taken along line AA' in FIG.
同図において、基体（Ｎ型半導体層）の表面ＫＩＣの入
力端子３が接触するＰ型層７が形成され、基体表面の酸
化膜（Ｓｉｎ、膜）９にの外部導出端子（ポンディング
パッド）２より接続される入力端子３との接続部分に上
記Ｐ型層７よりも深いＰ型層８を設けたものである。例
えば入力部がＮＰＮトランジスタのＰ型ベースである場
合、Ｐ型層７の深さを２．７μｍとすれば、外部端子２
より接続される入力端子３の接続するＰＷ７１８の深さ
を３．４〜３．５ａｍとする。ｔｆ）Ｐ型層８（Ｄ不Ｍ
物濃度はペースＰＷと同じ濃度又はそれより高い程度で
よい。In the figure, a P-type layer 7 is formed on the surface of the base (N-type semiconductor layer) with which the input terminal 3 of KIC contacts, and an external lead-out terminal (ponding pad) is formed on the oxide film (Sin, film) 9 on the surface of the base. A P-type layer 8, which is deeper than the P-type layer 7, is provided at the connection portion with the input terminal 3 connected to the P-type layer 7. For example, if the input part is a P-type base of an NPN transistor, and the depth of the P-type layer 7 is 2.7 μm, the external terminal 2
The depth of the PW 718 to which the input terminal 3 is connected is set to 3.4 to 3.5 am. tf) P-type layer 8 (D-type layer 8
The substance concentration may be the same as or higher than the pace PW.
上述した本発明によれば、下記の効果が得られる。According to the present invention described above, the following effects can be obtained.
（１） 入力端子コンタクト部のＰｔｌｉ層を深く形
成することにより、従来Ｐ型層、を浅く形成した場合に
おころＡＪの合金現象の進行による破壊を低減して、静
電破壊耐性を向上することができる。例えばコンタクト
部のＰ型層を浅いままＫした場合、耐圧１００Ｖ程度で
、深いＰ＠層を設けた場合２１０ Ｖ程度とすることが
可能である。(1) By forming the Ptli layer deeply in the input terminal contact area, damage caused by the progression of the alloying phenomenon of the roller AJ is reduced when the conventional P-type layer is formed shallowly, and electrostatic damage resistance is improved. be able to. For example, if the P-type layer in the contact portion is kept shallow, the breakdown voltage can be about 100V, and if a deep P@ layer is provided, the breakdown voltage can be about 210V.
（２）深く形成するＰ型層はコンタクト部の面積だけち
ればよいから、従来の静電破壊防止素子等に比して内部
素子のコンタクト部の面積が小さくてすみ、チップの縮
小化ができる。例えば、イー１２層の深さを２．７μｍ
とした場合、在来の破壊防止ダイオード（第１図）の場
合に占める面積は５０×８５μｒｎ″、Ｐ型コンタクト
（第３図の場合）に占める面積は４０Ｘ４０（コンタク
ト部３０Ｘ３０）μ♂であるのに対し、深いＰ型層を設
ける本発明の場合は２０Ｘ２５（コンタクト部１０Ｘ１
５）μ♂と縮小できる。(2) Since the deeply formed P-type layer only needs to reduce the area of the contact part, the area of the contact part of the internal element is smaller than that of conventional electrostatic breakdown prevention elements, and the size of the chip can be reduced. can. For example, the depth of the E12 layer is 2.7 μm.
In this case, the area occupied by the conventional anti-destruction diode (Fig. 1) is 50 x 85 μrn'', and the area occupied by the P-type contact (in the case of Fig. 3) is 40 x 40 (contact part 30 x 30) μ♂. On the other hand, in the case of the present invention in which a deep P-type layer is provided,
5) Can be reduced to μ♂.
本発明は前記実施例に限定されず下記のような変形例を
有する。The present invention is not limited to the above-mentioned embodiments, but has the following modifications.
（１） 深く形成するＰｉ１層はアイソレージ■？（
素子分離）用Ｐｇ″層を使ってもよい。ただしこの場合
ｐＨ層はＮ＋型堀込層によりＰ型基板から隔離され【い
ることが必要である。(1) Is the deeply formed Pi1 layer an isolation ■? (
A Pg'' layer for device isolation may also be used. However, in this case, the pH layer must be isolated from the P-type substrate by an N+ type digging layer.
本発明はＩＣの入力端子にペースＰ型層を使用する全て
の場合に適用することができ１％にバイポーラＩＣ，バ
イポーラＭＯ８ＩＣに応用することができる。The present invention can be applied to all cases where a pace P type layer is used for the input terminal of an IC, and can be applied to bipolar ICs and bipolar MO8 ICs in 1%.
第１図乃至第３図はこれまでのＩＣにおける静電破壊防
止構造の例を示す各部分平面図。
第４図は本発明によるＩＣの靜電破壊防正楕′造′を示
す部分平面図、
第５図は！！４図におけるＡ−ＡｗＴ［図である。
１晶基板、２・・・外部導出端子（パッド）、３・・・
入力端子、７・・ベースＰｆｉｌ＠ｉ、８・・・深いＰ
型層。
代理人 弁理士 薄 １）利 幸FIGS. 1 to 3 are partial plan views showing examples of electrostatic damage prevention structures in conventional ICs. Figure 4 is a partial plan view showing the electrostatic damage prevention elliptical structure of an IC according to the present invention, and Figure 5 is! ! A-AwT in Fig. 4 [Fig. 1 Crystal substrate, 2... External lead terminal (pad), 3...
Input terminal, 7...Base Pfil@i, 8...Deep P
Type layer. Agent Patent Attorney Susuki 1) Toshiyuki
Claims (1)
れ、この回路の入力端子に基体表面層と反対の導電型の
拡散層を有する半導体装置において、上記基体上の外部
導出端子より接続される入力端子への接続部分の拡散層
のみを核拡散層の他の部分より深く形成したことを特徴
とする半導体装置。 ２、基体の表面層をＮ型Ｓｉ層とし１反対導電型の拡散
層を特徴とする特許請求の範囲第１項に記載の半導体装
置。[Claims] 16. In a semiconductor device in which a semiconductor internal circuit is formed on a surface layer of a semiconductor substrate, and an input terminal of this circuit has a diffusion layer of a conductivity type opposite to that of the substrate surface layer, an external lead-out terminal on the substrate 1. A semiconductor device characterized in that only a portion of the diffusion layer connected to an input terminal that is connected to the nuclear diffusion layer is formed deeper than other portions of the nuclear diffusion layer. 2. The semiconductor device according to claim 1, wherein the surface layer of the base is an N-type Si layer and has a diffusion layer of an opposite conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57083099A JPS58200565A (en) | 1982-05-19 | 1982-05-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57083099A JPS58200565A (en) | 1982-05-19 | 1982-05-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58200565A true JPS58200565A (en) | 1983-11-22 |
Family
ID=13792735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57083099A Pending JPS58200565A (en) | 1982-05-19 | 1982-05-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58200565A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119562A (en) * | 1986-11-07 | 1988-05-24 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-05-19 JP JP57083099A patent/JPS58200565A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119562A (en) * | 1986-11-07 | 1988-05-24 | Toshiba Corp | Semiconductor device |
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