JPS58200567A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS58200567A
JPS58200567A JP57083098A JP8309882A JPS58200567A JP S58200567 A JPS58200567 A JP S58200567A JP 57083098 A JP57083098 A JP 57083098A JP 8309882 A JP8309882 A JP 8309882A JP S58200567 A JPS58200567 A JP S58200567A
Authority
JP
Japan
Prior art keywords
bonding pad
output
region
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57083098A
Other languages
Japanese (ja)
Inventor
Kiwa Yanagiya
柳屋　喜和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP57083098A priority Critical patent/JPS58200567A/en
Publication of JPS58200567A publication Critical patent/JPS58200567A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Wire Bonding (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To contrive to reduce the size of semiconductor chips by a method wherein the collector terminal of an output transistor and a bonding pad are formed within an island region. CONSTITUTION:An N<+> type buried layer 8 in the output transistor element Q1 is extended immediately under the part serving as the bonding pad, and the P<+> diffused layer 9 for isolation is formed in the outer periphery, thus an island region of the same potential is constituted. An N<+> diffused region 10 is extended immediately under the bonding pad and made to contact the N<+> buried layer 8, and accordingly the part of element internal resistance is reduced. The N<+> diffused region 11 for collector electrode take-out is formed also within the same range and insulated by a SiO2 film 12. The output bonding pad is used to take out collector terminal voltage to the outside, and the potentials of the transistor element and the bonding pad are always equal, therefore it is not necessary at a ll to form them in separated island regions.

Description

【発明の詳細な説明】 （８）発明の利用分野 本発明は、半導体集積回路装置、特に′ＴＴ　Ｌ（Ｔｒ
ａｎｓ　ｉｓ　ｔｅｒ−Ｔｒａｎｓｉｓｔｅｒ−Ｌｏｇ
ｉｃ）を構成する半導体集積回路装置（以下ＴＴＬ−Ｉ
Ｃと呼ぶ）に関するものである。Detailed Description of the Invention (8) Field of Application of the Invention The present invention relates to semiconductor integrated circuit devices, particularly 'TTL (Tr
ans is ter-Transister-Log
IC) constitutes a semiconductor integrated circuit device (hereinafter referred to as TTL-I
(referred to as C).

（ｂｌ従来技術 従来、第１図のような出力回路を有するＴＴしＩＣに於
て、出力段として用いるトランジスタ素子Ｑ、は、第２
図および第３図に示すように、その素子上をグランド配
線（ＧＮＤ）や電源配線（ｖｃｏ）等を通過させるため
、出力トランジスタＱ。(bl Prior Art) Conventionally, in a TT IC having an output circuit as shown in FIG. 1, the transistor element Q used as an output stage is
As shown in the figure and FIG. 3, the output transistor Q is used to pass ground wiring (GND), power supply wiring (VCO), etc. over the element.

の上段にあるダーリントン回路（ＤＣ）のエミッタ端子
に接続するためのコレクタ端子１と、出方用ポンデイン
グパツド５に接続するためのコレクタ端子４０２つの同
電位コレクタ端子が必ｒとなる。しかも、第３図から明
らかなように、出力ボンディングパッドのための領域６
と、出方トランジスタの領域７とが各々別位置に存在す
る構造となりている。Two collector terminals with the same potential are required: a collector terminal 1 for connecting to the emitter terminal of the Darlington circuit (DC) in the upper stage of the circuit, and a collector terminal 40 for connecting to the output ponding pad 5. Moreover, as is clear from FIG. 3, the area 6 for the output bonding pad
The structure is such that the region 7 and the region 7 of the output transistor are located at different positions.

このようなこれまでのＴＴＬ−ＩＣでは半導体ペレット
上での素子Ｑ１が占有する領域が大きくなる構造である
ため、ペレットサイズが大きくなることが欠点である。Such conventional TTL-ICs have a structure in which the area occupied by the element Q1 on the semiconductor pellet becomes large, so that the disadvantage is that the pellet size becomes large.

本発明はこのような欠点をなくすため、不必要なスペー
スとなる部分をＱＩＪ除することによってチップサイズ
を小さくできるＴＴＬ−ＩＣの提供を目的とする。In order to eliminate such drawbacks, the present invention aims to provide a TTL-IC whose chip size can be reduced by QIJ-dividing the unnecessary space.

本発明の要旨とするところは、半導体表面に形成された
出力トランジスタのコレクタ端子とポンデイングパツド
を一つの島領域内に形成することにより、半導体チップ
サイズの低減をはがることにある。The gist of the present invention is to reduce the size of a semiconductor chip by forming a collector terminal and a ponding pad of an output transistor formed on a semiconductor surface within one island region.

以下、本発明を実施例に従って、その内容を具体的に説
明する。Hereinafter, the present invention will be specifically described in accordance with examples.

第４図、第５図に示すように、ポンディングパッドとな
る部分の直下に出力トランジスタ素子Ｑ。As shown in FIGS. 4 and 5, the output transistor element Q is placed directly below the portion that will become the bonding pad.

内部のＮ＋　ｍ込層８を延長し、ポンディングパッドと
トランジスタ素子の外周にアイソレージ■ン用Ｐ＋拡散
層９を形成し、同電位の一つの島領域を構成する。The internal N+ m-containing layer 8 is extended, and a P+ diffusion layer 9 for isolating is formed around the bonding pad and the outer periphery of the transistor element, thereby forming one island region having the same potential.

この場合Ｎ＋塊込層８と同様、ポンディングパッド直下
までＮ＋拡散領域１０を広げ、ｒ厘込層８に接触させ、
素子内部抵抗分を減少させる。In this case, similarly to the N+ lump layer 8, the N+ diffusion region 10 is expanded to just below the bonding pad, brought into contact with the r lump layer 8,
Reduce element internal resistance.

また、コレクタ電極取り出し用虻拡散領域１１も同範囲
内に形成し、ＳｉＱ、ｌ［１２により絶縁させた状態で
ポンディングパッド配線を行なう位置にコンタクトホー
ルなあけてコレクタ端子とポンディングパッドとを共有
：したトランジスタ素子を形成する。In addition, a dovetail diffusion region 11 for taking out the collector electrode is also formed within the same range, and a contact hole is made at the position where the bonding pad wiring is to be performed while insulated by SiQ, L [12] to connect the collector terminal and the bonding pad. Shared: Forms a transistor element.

以上、実施例で述べた本発明によるＴＴＬ−ＩＣにおい
て、出力用ポンディングパッドは、トランジスタ素子の
コレクタ端子に生じる電圧を外部へ取り出すためのもの
であり、トランジスタ素子とポンディングパッドの電位
は常に等しい。As mentioned above, in the TTL-IC according to the present invention described in the embodiments, the output bonding pad is for taking out the voltage generated at the collector terminal of the transistor element to the outside, and the potential of the transistor element and the bonding pad is always equal.

故に、ポンディングパッドとトランジスタ素子を別個の
島領域とする必要性は全くなく、これまでの半導体装置
で用いたレイプラトルールはこの発明の素子の場合には
不要となり、そのためペレットサイズを低減することが
可能となる。という効果が得られる。Therefore, there is no need for the bonding pad and the transistor element to be separate island regions, and the lay plate rule used in conventional semiconductor devices is unnecessary in the case of the device of the present invention, thereby reducing the pellet size. becomes possible. This effect can be obtained.

本発明はこれ以外に変形例・応用例として、出力インパ
ークトランシスタ素子の面積が大きい素子を使用したバ
ッファ系や、出力趨子数が多いＴＴＬ−ＬＳＩ等に有効
である。In addition to this, the present invention is also effective in buffer systems using output impact transistor elements having a large area, TTL-LSIs having a large number of output traces, etc. as modifications and applications.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、ＴＴＬ−１ｃの出力回路図である。 ＃！２図は、第１図の出力回路中の出力トランジンタＱ
、を構成する従来の半導体集積回路装置の一部を示す部
分平面図である。 第３図は、第２図に示した半導体集積回路装置のｈ−Ａ
切断断面図である。 第４図は、出力トランジスタＱ１を構成する本発明の半
導体集積回路装置の一部を示す部分平面図である。 第５図は、第４図に示した半導体集積回路装置のＢ　−
Ｂ’切断断面図である。 １・・・コレクタ端子、２・・・ベース端子、３・・・
エミッタ端子、４・・・コレクタ端子、５・・・出力用
ポンディングパッド、６・・・出力用ポンディングパッ
ドのための領域、７・・・出力トランジスタ領域、８・
・・Ｎ＋埋込層、９・・・アイソレージｌン用Ｐ＋拡散
層、ｌＯ・・・虻拡散領域、１１・・・コレクタ電極取
り出し用Ｎ＋拡散層、１２・・・ＳｉＯ意属。 代理人　弁理士　　薄　１）利　幸 第　　１　　図 Ｌ−−０，−」FIG. 1 is an output circuit diagram of TTL-1c. #! Figure 2 shows the output transistor Q in the output circuit of Figure 1.
1 is a partial plan view showing a part of a conventional semiconductor integrated circuit device that constitutes a semiconductor integrated circuit device. FIG. 3 shows the h-A of the semiconductor integrated circuit device shown in FIG.
FIG. FIG. 4 is a partial plan view showing a part of the semiconductor integrated circuit device of the present invention that constitutes the output transistor Q1. FIG. 5 shows B − of the semiconductor integrated circuit device shown in FIG.
B' is a cut sectional view. 1... Collector terminal, 2... Base terminal, 3...
Emitter terminal, 4... Collector terminal, 5... Output bonding pad, 6... Area for output bonding pad, 7... Output transistor area, 8...
. . . N+ buried layer, 9 . . . P+ diffusion layer for isolation, 1O . . . Latch diffusion region, 11 . Agent Patent Attorney Susuki 1) Toshiyuki Dai 1 Figure L--0,-"

Claims (1)

【特許請求の範囲】[Claims] 半導体基体表面に形成された一つの島（領域）内に出力
用トランジスタが構成され、その島（領域）上にそのト
ランジスタの所定領域に電気的に接続される出力用ポン
デイングパツドが設けられていることを特徴とする半導
体集積回路装置。An output transistor is formed within one island (region) formed on the surface of the semiconductor substrate, and an output ponding pad is provided on the island (region) to be electrically connected to a predetermined region of the transistor. A semiconductor integrated circuit device characterized by:
JP57083098A 1982-05-19 1982-05-19 Semiconductor integrated circuit device Pending JPS58200567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57083098A JPS58200567A (en) 1982-05-19 1982-05-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57083098A JPS58200567A (en) 1982-05-19 1982-05-19 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58200567A true JPS58200567A (en) 1983-11-22

Family

ID=13792705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57083098A Pending JPS58200567A (en) 1982-05-19 1982-05-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58200567A (en)

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