JPS58200631A - Phase controlling circuit - Google Patents

Abstract

PURPOSE:To attain the accurate phase control, by frequency-dividing a clock pulse into 1/2, synchronizing a summing pulse with a pulse inverting the clock pulse and inputting the frequency-divided pulse and the synchronized pulse to an exclusive OR. CONSTITUTION:When the clock pulse cl1 is inputted to a frequency divider 11, the frequency is frequency-divided into a half and signals c, d having different phase by 180 deg. are generated. When a summing pulse +P from a distributing circuit is inputted to a pulsizing circuit 23 at an arbitrary time, the pulse +P is synchronized at the leading of the inverted pulse (f) and the synchronized signal (g) is outputted from the pulsizing circuit 23. On the other hand, an output signal (h) from a pulsizing circuit 25 and an outut signal k1 of an FF26 go to a high potential, the other input signal (d) is inverted and a signal m1 is obtained from an NAND circuit 27. Further, the signals (g) and m1 are inputted to the exclusive OR circuit 24 and a signal n1 of a low potential is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control circuit, particularly a phase control circuit suitable for performing phase modulation using addition pulses and subtraction pulses. Devices that perform various types of control depending on the conditions are used as control devices.As an example of such a control device, a servo mechanism that controls position will be illustrated below.

In Figure 1 of the plane, 1 is a servo motor, 2 is integrated with the servo motor 1, and its rotation controls the position t11, and 3 is connected to the fubo motor 1, and its rotation produces a position 8gI proportional to the rotation angle. 〇 On the other hand, 4
A command signal generator for commanding the feed amount of the load 2;
5 is a distribution circuit which inputs a command value from the signal command It signal generator 4 and generates a pulse voltage according to this command value by calculation; 6 is a distribution circuit (command according to the pulse signal from i5) This is a phase change Jii11 circuit that modulates the phase. 1 is the adder (1141 is also an adder. A filter (b) path 9 inputs the difference signal and converts it into an F1 signal corresponding to the difference signal.
1 is amplified and the servo motor 1 is turned -J1i18 by an angle corresponding to this DC signal.O member 42&'@
When sending from the current position to the desired position, the command value corresponding to the position 1a is output from the command signal generator 14.
The 0-phase modulation circuit 6, which outputs the number of addition pulses or subtraction pulses according to the command value, outputs the command number according to the number of addition pulses or subtraction pulses according to the calculation of the distribution gl correction 5. Advancing or retarding the phase of the pulse. When the phase-modulated command pulse is input to the adder 7, a phase difference occurs between the phase of this command pulse and the phase signal corresponding to the current position output from the resolver 3, and the adder 7
outputs a signal with that phase difference. This signal is converted into a DC signal by the filter circuit 8, amplified by the amplifier 9, and rotates the serve motor 1 according to the phase difference. As the servo motor 1 rotates, the resolver 3 also rotates in the direction of decreasing the phase difference, and when the phase difference finally reaches O, the load 2 coupled to the servo motor 1 is adjusted to the desired value. reach the position.

Figure 2 shows a time chart that explains the phase advance or delay of the command pulse due to 1 addition pulse or subtraction pulse.
511 +11... is shown, and this clock pulse Ml is shown in Figure 2 (b).

Command pulse bl that changes at the rising edge of aH, odor, etc.

k) l a b island... is shown. Now, 4
Figure 2 (C) As shown in K 5, clock pulse II e
If we introduce addition no(Rus p) to 1g, the command pulse becomes 1
7g2 (d) As shown in K, the phase advances by 0 & 1 pulses, 0 inverse k, Figure 2 (e) If the clock pulse a is removed as shown in K, the command pulse becomes as shown in Figure 2 (f
) As shown in 5, the phase shifts by exactly l pulses.

In order to control the phase of one command pulse in this way, it is necessary to introduce a pulse into the reference clock pulse by an addition pulse, or to remove the pulse by a subtraction pulse. The circuit configuration is shown below. However, as will be described later, there is no problem when removing pulses, and trouble occurs when pulses are introduced.
In the figure, 11 inputs the clock pulse CJ1 [its JI
It is a frequency divider that divides the frequency of Il wave a into 9, and is 180' from each other.
Output signals c and dv with the same phase. 12 is an ANDI circuit which receives /■tsuku/(Rus cjl at one input terminal, and one output signal -51c of the divider 11 at the other input terminal, and outputs (No. 1 C121t) , 13 is
This is an AND circuit in which the clock pulse cJl is input to one input terminal, the other output signal d of the frequency divider 11 is input to the other input terminal, and outputs an output signal C122. Reference numeral 14 denotes a pulsing circuit to which the addition pulse 10P and the output signal C121 from the AND circuit 12 are input, and the addition pulse +P is synchronized with this by the signal cj21. 15 is an AND of the addition pulse 10P synchronized by the pulse generator 14
The output signal C122 from the circuit 13 is input, and the introduction pulse xpv output j7) AND circuit, 16 is the output signal C121 of the AND circuit 12 and the introduction pulse p from the AND circuit 15.
is input, and outputs a signal C obtained by adding the introduction pulse p.
This is an R circuit.

! i43 The operation of the conventional circuit shown in figure #! This will be explained with reference to the time chart shown in FIG.

When the lock pulse Cj1 is inputted to the divider 11 as shown in FIG. 4 (1), this pulse is divided into %"CC
4th signal Φ, (d) K shows that the phase is 18 to each other at 5.
0" different notes C, dv are output. These outputs are input to the KANDAND circuit 13 together with the clock pulse cjl, respectively, and the output signals Cj21.Cj22t- are generated, respectively. On the other hand, when the addition pulse +P enters the pulsing circuit 14, , which is synchronized with the signal C121 and outputs the signal command P as shown in [Fig. 4 σ) K. This output is AND(2) path 1
When the output signal C122 of No. 3 is input to the AND circuit 15, l1 in the signal C121 is inputted to the AND circuit 15.
Pegiharu x p introduced in the middle of the liI pulse
By manually inputting the output pulse p of the output signal to the output signal C121 of the AND circuit 12 and the OR circuit 16, an output signal in which K/<Rus p is introduced as shown in IIE4a(h)K is obtained. .

By the way, in order to quickly activate the load 2 shown in FIG. 111 (that is, to reduce the response characteristic t1'), the frequency of the clock pulse cjl must be increased.

HllC, it is necessary to increase the mav* in order to fine-tune the operation per pulse of load 2 and perform more precise position detection (that is, increase the resolution).
Increasing the number of j [is required not only in the servo mechanism illustrated in FIG. 1, but also in other general control devices.

However, in the conventional circuit configuration shown in Fig. 3, a large number of gate circuits are required to add the pulses, and when using a high frequency, a gate delay occurs and the pulses are miscounted, resulting in a phase difference. This has the disadvantage that accurate control cannot be performed.

An object of the present invention is to eliminate such drawbacks and provide a phase control circuit that can perform accurate phase control without gate delay.

In order to achieve this object, the present invention divides the basic clock pulse by XK, inverts this frequency pulse, and synchronizes the half cycle of the clock pulse with the inverted addition pulse. Exclusive O
The R circuit is characterized in that it is used as an input.

Hereinafter, the present invention will be explained in detail based on the embodiment shown in FIG.

In FIG. 5, numeral 11 is a divider that receives a clock pulse cjiv and divides its frequency into %, similar to the divider shown in the third factor, and outputs signals Qc and d having 180° different phases from each other. 22 is an inverter circuit which inverts the clock pulse C11 to generate an inverted pulse ftl'. 23
is a pulsing circuit to which the asynchronous addition pulse 10P and the inverted pulse f from the inverter (b) path 22 are input;
The addition pulse +P is synchronized with the inverted pulse f&c. 024 is Exclusive, where the converted signal g is output.
eO) tlPl path, into which the signal g from the pulse generator 23 and the output signal from the NANDl path 2T (described later) are input to obtain the desired signal n1 or signal n2. o25 is an asynchronous subtraction pulse -P and frequency division. This is a pulsing circuit into which the signal C:1 from the device 11 is input, and the subtraction pulse -P is synchronized with this by n1vc.

The pulse generator 25 outputs a synchronized signal. 26 is a free-lag flop circuit, whose terminal S receives the output signal of the pulse generator 25, its terminal T receives the signal d from the frequency divider 11, and its terminal LK receives a positive voltage (for example, +
5■) are applied respectively. 21 is 7 lip 70
It is a NAND circuit which inputs the output signal kl or signal of the tsugu 26 and the output signal d of the frequency divider 11, and its output signal m1 or signal rrJ is the above-mentioned Exclusive
This becomes the input for the OR (b) path.

Next, I will explain the operation of this circuit with reference to the time chart shown in the 6th factor.
(a) to (i) are time charts during addition of pulses by addition pulse◆PK, (a) shown on the right
, (b), (C) and (j) to (j) are time charts during pulse removal (subtraction) by subtraction pulse-PK.
, (C) Since the signals cjl, c, and d shown in K are common signals during addition and subtraction, they are indicated by dotted lines to indicate that they are the same signals on the left and right sides.

When the clock pulse CJl is input to the frequency divider 11, the divider divides the frequency by 3fK as shown in FIG.
At the same time, the inverter 22 inverts the clock pulse C11'4I and supplies this inverted pulse f)l to the pulse conversion (b) path 23. Now, when the addition pulse 10P from the distribution circuit shown in the sixth example (e) K is inputted to the pulse generation circuit 23 at an arbitrary time, this asynchronous addition pulse x
+P is synchronized at the rising edge of the inversion pulse f.

The pulse generation circuit 23 outputs this synchronized signal gv ratio, but this output signal g is shifted and synchronized by the at-S period with respect to the gastric pulse cljK, as shown in FIG. 6(f)K. ing. On the other hand, in this case, since there is no input of the subtraction pulse -P, the output signal of the pulse (tllalj125 and the output signal kl of the ARITUB 70 and TUB26 are at a high level. Therefore, one input of the NAND jl circuit T is at a high level. As a result, the NAND-ro 27
The other input signal d is the output signal of the pulsing circuit 23 as shown in Fig. 6(h) and the NANl) ii path 21.
Since the output signal m1 of is input, its output is as shown in Fig. 6 (
The signal n1 into which the pulse p is introduced is obtained as shown in i). In this way, the desired signal into which the introduction pulse p is inserted can be obtained.

Contrary to the above explanation, when an asynchronous subtraction pulse -P as shown in FIG. The output signal is synchronized by the signal C from the output signal C, and the output signal as shown in FIG. 6(G)K is obtained. Since this signal is input to the flip-flop terminal S, the output signal k11 of the flip-flop 26 is the As shown in Figure 6 (1), the level becomes low. Therefore, during this period NA
The output m1 of the ND circuit 27 is at a high level as shown in Fig. 6 (tn)K. On the other hand, in this case, the addition pulse to the pulse generator 23 is also at a high level, so the output signal n volume is equal to that period. As shown in FIG. 6(n), when looking only at the rising edge of the signal n■ shown in O, which is at a low level,
As shown in Fig. 11182(-)K, the state is exactly the same as when one pulse was removed in step 5, and the desired signal can be obtained.

Now, if we go back to the case of addition mentioned above, NAN
I) The d21st output signal is the signal d input to it.
This inverted signal is similar to signal C. Therefore, it is understood that the output signal g of the pulse circuit 23 and the output signal C whose frequency has been divided by 3fK by the frequency divider may be input to the pulse input terminal.

In this embodiment, lc Exclusive OR
A circuit V is provided, and its input signals include a signal obtained by synchronizing the addition pulse with the inverted pulse test of the subtraction pulse by a pulse conversion circuit, and a signal from a frequency divider, which is the signal of the pulse conversion circuit that inputs the subtraction pulse. At the same time, since the signal processed by the Fritsu 17021 circuit and the NAND circuit is used for 5K, there is no need to use a large number of gate circuits as seen in conventional circuit configurations, and accurate phase control without gate delay is achieved. be able to.

In the above explanation, we have described an example in which this phase control circuit is applied to a servo mechanism that performs position control, but the application is not limited to such a servo mechanism, and can be applied to any device that modulates the phase by pulses. can do.

As described above, in the present invention, the frequency of the clock pulse is divided into %, the addition pulse is synchronized with a pulse obtained by inverting the clock pulse, and this synchronized pulse and the above-mentioned 3iK frequency-divided pulse are exclusively OR
Since it is used as an input to the circuit, accurate phase control 141v without gate delay can be performed even at high frequencies.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a servo motor control circuit, Figures 2 (a) to (f) are time charts of pulses generated in the control circuit shown in Figure 1, and Figure 3 is a block diagram of a conventional phase control circuit. Figure 41 & (M) to (h) are time charts of pulses generated in the phase control circuit shown in Figure 3;
The figure is a block diagram of a phase control circuit according to an embodiment of the present invention,
6(a) to (rl) are time charts of pulses generated in the phase control circuit shown in FIG. 5. FIG. 11...h frequency divider, 22...inverter, 23...pulsing circuit, 24...group Ex
exclusive OR circuit. Fig. 1 tjA Fig. 2 Fig. 3

Claims (1)

[Claims] a frequency divider that divides the clock pulse into half; an inverter that inverts the clock pulse; and a pulse generator that synchronizes the asynchronous addition pulse by shifting it by a half period of the clock pulse with the output of the inverter; A phase control circuit comprising an exclusive off circuit which receives the output of the pulse generator and the divided period output as inputs.