JPS5821365A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5821365A JPS5821365A JP57050405A JP5040582A JPS5821365A JP S5821365 A JPS5821365 A JP S5821365A JP 57050405 A JP57050405 A JP 57050405A JP 5040582 A JP5040582 A JP 5040582A JP S5821365 A JPS5821365 A JP S5821365A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- resistance
- pattern
- resistor
- matched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は互いに整合を必要とする抵抗体を有する半導体
集積回路装置、4IK同一の周辺パターン分布を要する
抵抗体を複数個有する装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device having resistors that require mutual matching, and a device having a plurality of resistors that require the same 4IK peripheral pattern distribution.
半導体集積回路装置における抵抗体はフォトシン注入法
ま几ドープドオキサイド法等によシ選択的に行なわれる
。とくに抵抗パターンはマスクパターンを用いてエツチ
ングにより作られる。ボロン、リン、アンチモンおよび
ヒ素等の不純物を導入して抵抗領域を形成する方法も取
られる。Resistors in semiconductor integrated circuit devices are selectively formed by a photosin injection method, a doped oxide method, or the like. In particular, the resistor pattern is created by etching using a mask pattern. A method of forming a resistance region by introducing impurities such as boron, phosphorus, antimony, and arsenic is also used.
電子回路上、%に特性が一致した。即ち整合を必要とす
る半導体素子を形成する場合は、従来においては不純物
拡散時の層抵抗のばらつ7きおよび拡散マスク製作時の
素子寸法のばらつきの影響を勇躍して2つ以上の整合素
子の配置をできるだけ隣接させ、かつパターンの形状お
よび方向性管間1−にするように配膳してパターン設計
が行なわれてい九〇
しかしこの配膳だけでは十分な兼合が得られなかった。On the electronic circuit, the characteristics matched %. In other words, when forming a semiconductor element that requires matching, conventionally, two or more matching elements are used to overcome the effects of variations in layer resistance during impurity diffusion and variations in element dimensions during diffusion mask fabrication. Pattern design has been carried out by arranging the pipes so that the pipes are arranged as close as possible, and the shape and direction of the pattern are 1-.
これは写真食刻の際のパターン相互の干渉による素子寸
法の設計値に対するずれを補正することが出来ない几め
と考えられる。すなわち写1 真食刻技術においてマス
クに描かれたパ夛−ンは密着露光法あるいは投影露光法
等によってシリコン基板上に塗布されたフォトレジスト
(感光性樹脂)に焼き付けられるが、この時素子パター
ン間の間隔の広さが異なると、光が照射された部分が光
重合反応を起して硬化し、光が照射されない部分が現像
により除去されるネガタイプのフォトレジストを使用し
た場合、マスクの暗部が素子パターンと一致する。従っ
て並列に並ぶ3個の抵抗体を形成する際、抵抗パターン
以外の部分に光が照射される。この定め平面的にみて左
右両端に位置する抵抗パターンより外側にある露光領域
は抵抗パターンによってはさまれt部分(中央の抵抗パ
ターンの両側)の露光領域よりもLi。この結果光の照
射量が領域によりて異な9てしまい、外側の領域には多
くの光があた9重合度は密となるがパターン間の領域は
照射量が少なく重合度が粗に壜る◎しかも微細化に伴り
てパターン間隔が狭くなる程その重合度は更に小さくな
る。従うて現像時の定着(リンス)処理において十分に
重合されなかった部分(抵抗パターンによってはさまれ
た部分)が溶解されせまくなってしまう。一方1両端に
位置する抵抗パターンの外側は十分に重合されているた
め、上記の溶解は少ない。従ってどうしても中央の抵抗
パターンの巾が両端のそれよりも広くなって抵抗値にバ
ラツキが生じてしまう。This is considered to be due to the fact that it is not possible to correct deviations in element dimensions from design values due to interference between patterns during photoetching. In other words, Photo 1: In the true etching technique, patterns drawn on a mask are printed onto a photoresist (photosensitive resin) coated on a silicon substrate by a contact exposure method or a projection exposure method, but at this time the element pattern is When using a negative type photoresist, the areas exposed to light will undergo a photopolymerization reaction and harden, and the areas not exposed to light will be removed by development. matches the element pattern. Therefore, when forming three resistors arranged in parallel, parts other than the resistor pattern are irradiated with light. The exposed areas outside the resistor patterns located at both left and right ends when viewed from the defined plane are more Li than the exposed areas at the t portions (both sides of the central resistor pattern) that are sandwiched between the resistor patterns. As a result, the amount of light irradiated varies depending on the area, and the outer regions receive a lot of light and the degree of polymerization is dense, but the area between the patterns has a small amount of irradiation and the degree of polymerization is coarse. ◎Moreover, as the pattern spacing becomes narrower with miniaturization, the degree of polymerization further decreases. Therefore, in the fixing (rinsing) process during development, the portions that were not sufficiently polymerized (the portions sandwiched between the resistor patterns) are not dissolved. On the other hand, since the outside of the resistance pattern located at both ends of the resistor pattern is sufficiently polymerized, the above-mentioned dissolution is small. Therefore, the width of the resistor pattern at the center inevitably becomes wider than that at both ends, resulting in variations in resistance values.
一方、ポジ型レジストを使う場合、これは感光された部
分が除去されるので、マスクの明部が抵抗パターンと一
致する。従りてこの場合は露光されるレジスト領域の面
積は等しい。しかし抵抗パターンによって両側がはさま
れた暗部に相当する部分(中央の抵抗パターンの両II
)へはlI接する抵抗パターン(明部)からの光の回り
込み、および屈折し九九の反射によってパターン間がせ
まいために相互干渉をうけて不l!に露光されてしまう
。On the other hand, when using a positive resist, the exposed areas are removed so that the bright areas of the mask match the resistor pattern. Therefore, in this case, the areas of the exposed resist regions are equal. However, the part corresponding to the dark area sandwiched on both sides by the resistor pattern (both II of the center resistor pattern)
), the light goes around from the resistor pattern (bright part) that is in contact with lI, and due to refraction and reflection, the patterns are narrow and mutual interference occurs. exposed to light.
一方9両端の抵抗パターンはその外側からの光の影響を
受けなi九め、不要露光紘約半になる。その結果やは9
中央の抵抗パターンの巾がその両端の抵抗パターンの巾
よりも広くなってしまい、抵抗値のバラツキが大きくな
ってしまう。On the other hand, the resistor patterns at both ends of the resistor pattern are unaffected by light from the outside, and the unnecessary exposure is approximately half as high. The result is 9
The width of the resistor pattern at the center becomes wider than the widths of the resistor patterns at both ends, resulting in large variations in resistance values.
従って従来の写真食刻法によシ例えば同−巾を持つ3本
のスリットを平行に等間隔て韮ぺた場合。Therefore, when using the conventional photolithography method, for example, three slits having the same width are formed parallel to each other at equal intervals.
焼き付けられたレジストパターンでは中央のスリ、トの
巾はその両側のスリットの巾より広くなる〇このように
従来整合を必要とする半導体素子を形成する際勇躍した
パターンの配置だけでは希望の整合が取れなくなる。さ
らにマスク製作時におけるパターンの転写においても上
記現像が椰こりマスクパターン自身も設計通ルの寸法が
得られなくなり、パターン寸法の眩計値からのずれt増
大させる乙とになる◎
この発明の目的は著しく整合がとれた素子が得られる構
造の半導体集積1路装置1提供するにあるO
本発明によれば互に整合されるべき抵抗体の周辺パター
ン分布の条件が同一になるように本来の抵抗パターンの
他に@路上側ら関係のない非抵抗パターンが付加される
。In the baked resist pattern, the width of the center slit is wider than the width of the slits on both sides. In this way, when forming a semiconductor device that requires conventional alignment, it is difficult to achieve the desired alignment by simply arranging the pattern. I can't get it. Furthermore, during the transfer of the pattern during mask production, the above-mentioned development will cause the mask pattern itself to not have the dimensions as designed, which will increase the deviation of the pattern dimension from the dazzle value. Object of the Invention According to the present invention, the conditions of the peripheral pattern distribution of the resistors to be mutually matched are made the same, so that In addition to the resistance pattern, an unrelated non-resistance pattern from the road side is added.
次に図ifiを参照してこの発明による半導体集積回路
I!直の例tit明しよう◎
1g1図は抵抗値が1:2の比であることが要求される
抵抗素子を形成する場合で、同形、同寸法を持つ3つの
拡散抵抗素子A、B、eが同一間隔で平行にiべられて
半導体基[K形成される。抵抗素子A、Bの各一端部は
アルミニウム配@IKコンタクト部2,3tそれ(れ通
じて接続され。Next, referring to FIG. ifi, the semiconductor integrated circuit I according to the present invention! Let's clarify a direct example. ◎ Figure 1g1 shows a case where a resistance element is formed whose resistance value is required to have a ratio of 1:2, and three diffused resistance elements A, B, and e having the same shape and dimensions are formed. Semiconductor groups [K] are formed by parallel etching at equal intervals. One end of each of the resistive elements A and B is connected through the aluminum contact parts 2 and 3t.
他端部はEII4にコンタクト部5.6tそれぞれ通じ
て接続される。抵抗素子Cの両端部はそれぞれコンタク
)$6.7を通じて配lll8 、9に接続される。抵
抗素子A、B、eは同形、同寸法であり、同−不純物談
度であるから、その各抵抗値を几とすれば配置1!1.
4間の抵抗値BI2.配線8゜9間の抵抗値は几となる
。しかしながら従来においては抵抗素子A、B、Ct厳
密に同形、同寸法とすることができなかった。The other end is connected to EII4 through contact portions 5.6t, respectively. Both ends of resistive element C are connected to traces 8 and 9 through contacts (6.7), respectively. Resistance elements A, B, and e have the same shape and size, and have the same impurity content, so if their respective resistance values are taken into account, the arrangement is 1!1.
The resistance value between BI2. The resistance value between the wires 8°9 is 几. However, in the past, it has not been possible to make the resistive elements A, B, and Ct exactly the same shape and size.
この発明においては抵抗素子A、B、Cの周辺パターン
分布が同一になるようにこれ等抵抗素子A、B、Cと回
路的(無関係の浮遊拡散領域DI。In this invention, in order to make the peripheral pattern distribution of the resistive elements A, B, and C the same, these resistive elements A, B, and C are connected to each other in a circuit (unrelated floating diffusion region DI).
D2が設けられる。拡散領域D1は抵抗素子Aの素子B
と反対側において素子A、B間の間隔d1と同一の間隔
dlをもって互に平行に対向して配され、かつその長さ
Jlは素子i、B、eのそれと同一とされる。同様に抵
抗素子Cの素子Bと反対側において間隔alt−保ち互
に平行対向し、長さ11の浮遊拡散領域り雪が設けられ
る。領域Dt 、Diの巾は抵抗素子A、B、Cの巾と
同一にする必要はない。D2 is provided. Diffusion region D1 is element B of resistance element A.
On the opposite side, the elements A and B are arranged parallel to each other with an interval dl equal to the interval d1 between them, and their length Jl is the same as that of elements i, B, and e. Similarly, floating diffusion regions having a length of 11 are provided on the opposite side of the resistive element C from the element B, parallel to each other with an interval ALT. The widths of the regions Dt and Di do not need to be the same as the widths of the resistive elements A, B, and C.
上述の構成によれば抵抗素子A、BおよびCの各パター
ンの周辺パターン分布の条件は全く同じとな9.抵抗素
子ム、B、CI形成する友めのレジストパターンと同時
に浮遊領域Dt、D!に対するレジストパターンも同時
に形成され、このため露光−現像時に受ける各素子人、
B、CK対する影響は全く同一とな9.同一寸法の抵抗
素千人。According to the above configuration, the peripheral pattern distribution conditions of each pattern of resistive elements A, B, and C are exactly the same9. Floating regions Dt, D! at the same time as the friend resist patterns forming resistive elements M, B, CI! A resist pattern for each element is also formed at the same time.
The effects on B and CK are exactly the same9. A thousand resistors with the same dimensions.
B、Cが得られ、素子A、Cの6巾より素子Bの巾が大
となるようなことはない。B and C are obtained, and the width of element B is never larger than the six widths of elements A and C.
182図においては互に平行配列された抵抗素子ム、B
の外側に浮遊拡散領域Dt、Dzt−形成し。In Fig. 182, resistor elements arranged in parallel to each other, B
Floating diffusion regions Dt, Dzt- are formed outside of.
この抵抗素子ム、Bの両端をそれぞれ配置@1 、4に
接続して並列抵抗とされる。これ等抵抗素子ム。Both ends of the resistance elements M and B are connected to the arrangement @1 and 4, respectively, to form a parallel resistance. These are resistive elements.
Bと離してこれと整合される宍き抵抗素子Cが形成され
、その際、抵抗素子Cの両側に浮遊拡散領域DB、D4
が同時に形成される。領域DI素子網。A resistive resistive element C is formed apart from and matched with B, with floating diffusion regions DB, D4 on both sides of the resistive element C.
are formed simultaneously. Area DI element network.
素子A、B間、素子B領域D8り、素子Cと領域Dz及
びD4との各間はすべて同一とされる。この場合も抵抗
素子A、B、Cの寸法を厳1!!に一致させることがで
きる。第3図は111図において浮遊領域D2の代りに
他の素子E−IIX形成された場合である。素子E及び
0間の間隔はdlとされる。The distances between elements A and B, between element B region D8, and between element C and regions Dz and D4 are all the same. In this case as well, the dimensions of resistance elements A, B, and C must be strictly 1! ! can be matched. FIG. 3 shows a case where another element E-IIX is formed in place of the floating region D2 in FIG. 111. The spacing between elements E and 0 is dl.
−例として抵抗パターン巾が10s、パターン間隔が1
0μの場合、東京応化工業−のネガレジスト(L)MR
−83)を用い、シリコン酸化膜の厚さが、0.7μ、
エツチング液としてフッ酸:フッ化アンモニウムがl:
6のバッフアートi(Fで形成した従来の抵抗体では整
合のパラツ中が両端と中央とで2〜5Xあう九が1本実
施例ではIX以内だった@又、上述ではネガタイプのフ
ォトレジストを用いt場合の例であり1wJち例えば第
1図においてパターン形成1福の露光−現曹後は、パタ
ーンA、B、C,DI及びD2の部分にはレジストはな
く、その他の部分に露光されて重合したレジストが残っ
ているが、これと逆にパターンA。-For example, the resistance pattern width is 10s and the pattern interval is 1
In the case of 0μ, Tokyo Ohka Kogyo negative resist (L) MR
-83), the thickness of the silicon oxide film is 0.7μ,
Hydrofluoric acid and ammonium fluoride were used as the etching solution.
In the conventional resistor formed with the buffer art i (F) of 6, the matching part between both ends and the center was 2 to 5X, which was within IX in this example. For example, in FIG. 1, after pattern formation, after exposure and development, there is no resist in the areas of patterns A, B, C, DI, and D2, and the other areas are exposed. The polymerized resist remains, but pattern A is the opposite.
B、e、Dt、Diの部分に光照射され、その部分が除
去されるポジタイプフォトレジストを用いる場合にも本
発明は適用される。The present invention is also applicable to the case of using a positive type photoresist in which the B, e, Dt, and Di portions are irradiated with light and those portions are removed.
s1図は本発明i&置の一例である整合を必要とする2
つの抵抗素子を並べて配置した平面図、第2図は整合を
必袂とする抵抗素子を単独に配置し几場合の平面図、第
3図は本発明装置の更に他の例を示す平面図でめる。
A、13.G :半纒体素子としての抵抗素子。
L)l、L)2.D3.D4:浮遊拡散領域図面の浄書
(内容に変更なし)
輩 1 悶
寥 2 田
l
手続補正書(1式)
/
1、事件の表示 昭和57年 特 許 願第504
08号2、発明の名称 半導体集積回路装置3、
補正をする者
事件との関係 出 願 人東京都港区芝五
丁目33番1号
6、補正の対象
明細書および図面
7 補正の内容The s1 diagram is an example of the invention i & 2 which requires alignment.
FIG. 2 is a plan view showing a case in which two resistance elements are arranged side by side, FIG. Melt. A, 13. G: Resistance element as a semicircular element. L)l, L)2. D3. D4: Engraving of floating diffusion region drawing (no change in content) 1. 2. Procedural amendment (1 set) / 1. Indication of incident 1988 Patent Application No. 504
No. 08 No. 2, Title of the invention: Semiconductor integrated circuit device 3,
Relationship with the case of the person making the amendment Applicant: 5-33-1-6, Shiba 5-chome, Minato-ku, Tokyo Description and drawings to be amended 7 Contents of the amendment
Claims (1)
体を備え、これら複数の抵抗体のうちその左右のいづれ
か一方に隣接する抵抗体を有しない抵抗体に対して、当
該抵抗体と同一材質よりなる非抵抗体を配置し友ことを
特徴とする半導体集積回路装置。Each resistor has a strip-shaped resistor of Ila having substantially the same resistance, and for a resistor that does not have a resistor adjacent to either the left or right side of the plurality of resistors, the resistor is identical to the resistor. A semiconductor integrated circuit device characterized by having a non-resistive element made of a material arranged therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050405A JPS5821365A (en) | 1982-03-29 | 1982-03-29 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050405A JPS5821365A (en) | 1982-03-29 | 1982-03-29 | Semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP48097567A Division JPS5947463B2 (en) | 1973-08-29 | 1973-08-29 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5821365A true JPS5821365A (en) | 1983-02-08 |
| JPH022296B2 JPH022296B2 (en) | 1990-01-17 |
Family
ID=12857949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57050405A Granted JPS5821365A (en) | 1982-03-29 | 1982-03-29 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821365A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6180519U (en) * | 1984-10-31 | 1986-05-29 | ||
| JPH0269972A (en) * | 1988-09-05 | 1990-03-08 | Seiko Epson Corp | semiconductor integrated device |
| JPH0521718A (en) * | 1991-07-10 | 1993-01-29 | Mitsubishi Electric Corp | R-2R ladder resistance device |
-
1982
- 1982-03-29 JP JP57050405A patent/JPS5821365A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6180519U (en) * | 1984-10-31 | 1986-05-29 | ||
| JPH0269972A (en) * | 1988-09-05 | 1990-03-08 | Seiko Epson Corp | semiconductor integrated device |
| JPH0521718A (en) * | 1991-07-10 | 1993-01-29 | Mitsubishi Electric Corp | R-2R ladder resistance device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH022296B2 (en) | 1990-01-17 |
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