JPS58215567A - Rectangular wave control circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for convertional weighting on upcount operation, by processing simultaneously and easily various measurements of external pulses and the output of a control pulse signal, and setting data in a counting register on the bais of the down-count operation of a reference clock. CONSTITUTION:An increasing and decreasing device 2-0 operates on time-division basis under the control of a control circuit 2-1 to increase the contents of the 1st counter latch 1-1 by one, and decrease the contents of the 2nd counter latch 2-2 by one when a reference clock is inputted. Then, data corresponding to the width of a pulse signal is stored in the counting register 2-3 through an internal data bus 1-3. When a borrow is outputted during a decrease in the contents of the 2nd counter latch 2-2, a pulse output circuit changes an output terminal 1-6 in output state, and opens the 2nd transfer gate 2-4 simultaneously to transfer the contents of the counting register 2-3 to the 2nd counter latch.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rectangular wave control circuit that creates pulse output timing based on values set in a program and further measures the input timing of externally input pulses.

Control systems controlled by pulse signals are usually controlled by pulse input timing, pulse width, and number of pulses. When generating this highly controlled pulse signal,
A reference clock counting circuit is used that counts a special basic clock that serves as the reference clock to generate the necessary timing.

A conventionally used reference clock counting circuit will be explained with reference to the block diagram of FIG. 1 and the timing charts of FIGS. 2 to 4.

In the block diagram of FIG. 1, incrementer 1-0 increases the content of counter clutch 1-1 by +1 every time a reference clock is input. The comparison register 1-2 stores comparison data corresponding to the output timing of the pulse signal via the internal data bus 1-3. Comparator 1-4 compares the count value in up counter 1-1 with comparison register 1-
The comparison data in 2 are constantly compared, and when the two match, a match signal is output to the pulse circuit 1-5. Pulse output circuit 1
-5 changes the output state of the output terminal 1-6 every time a coincidence signal is input, and at the same time controls the clearing of the counter latch 1-1. When the external pulse signal is input to the input terminal 1-9, the transfer gate 1-8 transfers the contents of the counter latch 1-1 to the input register 1-7.
holds the timing at which this external pulse signal was input.

Data in input registers 1-7 can be read via internal data bus 1-3.

Figures 2, 3, and 4 show output terminals 1-6 when measuring the period of a rectangular wave input from input terminals 1-9, respectively.
12 is a timing chart when outputting control pulses from the image processing apparatus and performing image processing at the same time.

In the period measurement, in the timing chart of FIG. 2, when the first rising edge of the rectangular wave is input to the input terminal 1-9 at the timing tl, the transfer gate 1-8 opens.
The first count value at 1° of counter latte 1-1 is transferred to input register ]-7. Similarly, the next t2
When the second rising edge is input at the timing of
The second count value at 12 of counter latch 1-1 is transferred to input register 1-7. Square wave period T!
is this first. It is obtained by calculating the difference between the second count values q-. In the pulse output, in the block diagram of FIG. 1 and the timing chart of FIG. 3, comparison data corresponding to 1/2 of the period T2 is stored in the comparison register 1-2. The contents of the counter latch 1-1 and the comparison register 1-2 are compared by the comparator 1-4, and when a first match is detected at timing t3, a match signal is outputted to the pulse output circuit 1-5. The pulse output circuit 1-5 changes the output level to the output terminal 1-6 in synchronization with this coincidence signal, and at the same time clears the counter latte 1-1.

The counter 1-1 increases from 0 to 0 each time the reference clock is input. Next, when the comparator 1-4 detects the second match at timing 14, the pulse output circuit 1-5 changes the output 1/pel to the output terminal 1-6, and at the same time the counter latch 1-1ffi clear. The above operation is repeated and a rectangular wave whose level changes every time a match is detected is output from the output terminal 1-6.

In normal pulse control, it is very rare that one of the above-mentioned period measurement for the rectangular wave and the rectangular wave output are not performed. There is an increasing need to process both at the same time.

The operation when simultaneously performing the above-mentioned period measurement and pulse output using a conventional reference clock counting circuit will be explained with reference to the timing chart of FIG.

The method of measuring the period is exactly the same as the method explained using the timing chart of FIG. The pulse output method is that counter latch 1-1 counts up the reference clock and measures the period, so it is possible to clear counter latch 1-1 in synchronization with the coincidence signal output from comparator -4. This is not possible, so I am using another method to output pulses as shown below.

Comparator 1-4 connects counter latch 1-1 and comparison register 1
When the first match with -2 is detected at timing 16,
-Pulse output circuit 1-5 output terminal 1 at this timing.
Change the output level of -6.

However, counter latch 1-1 is not cleared.

At this time, the second
In order to obtain comparison data corresponding to the timing t7 at which a match should occur, the data corresponding to the timing t6 stored in the comparison register 1-2 and 1/1 of the synchronization T2 are used.
2 and the data corresponding to 2, and the result of this addition is newly stored in comparison register 1- as comparison data for the second match.
Set to 2. When a second coincidence signal is detected in synchronization with the next timing 17, comparison data corresponding to timing t8 is calculated and stored in the comparison register ]-2 again, and the same operation is repeated.

Although period measurement has been described as an example of measurement, measurement of pulse width and measurement of pulse input timing are similarly obtained by processing data held in the input register A-7.

As explained above, when a conventional reference clock counting circuit performs various measurements for external pulses and outputs control pulse signals at the same time, each time a coincidence signal indicating the change timing of the rectangular wave output is generated, the next coincidence is generated. The first disadvantage is that new comparison data must be set in preparation for The second drawback is that the comparison data to be set is not simply data corresponding to the period of the square wave, but must always be set as a sum of previous comparison data and weighted against the count value of the up counter. In addition to the up counter and comparison register,
The third drawback is that a comparator is required to detect a match between the two, which increases the hardware.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference clock counting circuit which eliminates the above drawbacks and minimizes the amount of hardware required.

The rectangular wave control circuit of the present invention includes a first latch that holds a count value of a reference clock, a second latch that holds an output timing value of an output rectangular wave, and a second latch that holds a count value of a reference clock, and a second latch that holds a count value of an output rectangular wave. It has a single increase/decrease that increases or decreases the content of the first latch and the content of the second latch by 1, and adjusts the input timing of the input rectangular wave to the input timing of the first latch at the time when the rectangular wave crosses λ. It is characterized in that the output timing of the output rectangular wave occurs at an overflow or underflow of data corresponding to the output timing held in the second latch.

Embodiments of the present invention will be described with reference to the block diagram in FIG. 5 to the timing chart in FIG. 7.

In the block diagram of FIG. 5, the tenth counter latch 1
-1. Internal bus 1-3. Pulse output circuit 1-5. Output terminal 1-6. Input register 1-7゜first transfer game) 1-
8. Input terminals 1-9 are similar to those described in the block diagram of FIG. The increase/decrease unit 2-0 operates in a time-division manner under the control of the control circuit 2-1, and when the reference clock is input, increases the content of the first counter latch 1-1 by 1, and further increases the content of the second counter latch 2-2. Decrement the content by 1.

Data corresponding to the width of the pulse signal is stored in the count register 2-3 via the internal data bus 1-3.

The pulse output circuit decrements the contents of the second counter latch 2-2 to change the output state of the output terminal 1-6 when a borrow is output, and simultaneously changes the output state of the output terminal 1-6.
At the same time, the second transfer gate 2-4 is opened and the contents of the count register 2-3 are transferred to the second counter clutch.

Next, the operation of the reference clock counting circuit according to the present invention will be explained with reference to the timing chart of FIG. The increase/decrease device 2-0 is used in a time-division manner according to the control signal output from the control circuit 2-1, and when the reference clock is input at timing t6, the first counter latch 1-0 is used during the period when the control signal is at a high level. 1 is incremented by 1, and the content of the second counter latch 2-2 is increased by 1 in the subsequent low level period.
decrease only. When the reference clock is input again at the next timing t7, the above operation is repeated again.

The operation of simultaneously performing period measurement and pulse output using the reference clock counting circuit according to the present invention will be described with reference to the timing chart of FIG.

The method of measuring the period is exactly the same as the method explained in the timing chart of FIG.
It is obtained by calculating the difference between the first count value and the second count value held at timing t2 within -1. The following operations are performed during pulse output. The count register 2-3 stores data corresponding to 1/2 of the output pulse period T2. The increase/decrement device 2-0 decreases the contents of the second counter latch 2-2 by one each time the reference clock is input. As a result of the decrease, the first
When a borrow is output, this borrow signal is output to the pulse output circuit 1-5. The pulse output circuit 1-5 changes the output level of the output terminal 1-6 in synchronization with this pollo signal, and at the same time opens the second transfer gate 2-4 and transfers the contents of the count register 2-3 to the second counter. Transferred to latch 2-2. Again, the second counter latch is decremented by one for each reference lock. When the increase/decrease unit 2-0 outputs the second borrow at the next timing t7, a rectangular wave whose level changes for each borrow signal is output from the output terminal 1-6, which repeats the same operation as above.

As explained above, the reference clock counting circuit according to the present invention can simultaneously and easily process various measurements of external pulses and the output of control pulse signals. In particular, in the output of the control pulse signal, the data set in the count register is based on down-counting of the reference clock, so there is no need to weight up-counting as in the conventional case.

Furthermore, there is no need to update the settings every time the output level changes, which can significantly reduce software effort.

In addition, in terms of hardware, there is no need for a comparator to detect coincidence between the counter and comparison register, making it possible to significantly reduce the amount of hardware compared to conventional systems, and it is capable of complex pulse signal processing functions. 1 chip, it has a very great practical effect on microcomputers.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional rectangular wave control circuit;
3 and 4 are timing diagrams showing the operation of FIG. 1, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 7 is a timing diagram showing the operation of FIG. 5. 1-0...Incrementer, 1-1...
First counter ratte, 1-2°/°゛°° comparison register, 1-3... Data bus, 1-4...
・Comparator, 1-5...Pulse output circuit, 1-6
...Output terminal, 1-7...Input register, 1-8...First transfer gate. 1-9...Input terminal, 2-o...Increase/decrease, 2-1...Control circuit, 2-2...
Second counter ratte, 2-3...count register, 2-4...second transfer gate. No-3:, ¥'＜,,=t ln1

Claims (1)

[Claims] The first latch holds the counted value of the reference clock, the second latch holds the output timing value of the output rectangular wave, and the first latch is used in a time-division manner each time the reference clock is input. It has a single increase/decrease that increases or decreases the content of the second latch by 1, and measures the input timing of the input square wave with the content of the first latch at the time the input square wave is input. The rectangular wave control circuit is characterized in that the output timing of the output rectangular wave is generated at an overflow or an underflow of the output timing value held in the second latch.