JPS5824751B2 - liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electro-optical display device, such as a liquid crystal display device, which operates at a relatively low frequency, and its application equipment.

The present invention is particularly applicable to small-sized portable devices such as electronic watches and calculators.
A configuration method that achieves low power consumption and low cost is provided.

In recent years, the functions of such devices have become increasingly complex, and a configuration system that satisfies these requirements is strongly desired.

In terms of low power consumption, there are favorable elements such as liquid crystal and C-MOS.

However, in the case of a wristwatch, the permissible power is extremely sensitive, so even if this element is used, it must be designed with great care.

FIG. 1 is a circuit diagram showing an example of an electronic timepiece using the present invention.

As described below, the present invention has a configuration in which segment electrodes of a display device are divided into at least two groups, and a display drive signal is once input to a shift register corresponding to each group, and then the segment electrodes are driven. Therefore, the count circuit uses a synchronous type circuit, which is convenient for transfer.

■ is a standard time oscillator consisting of a crystal oscillator, and ■ is a circuit that forms a timing pulse group and also serves as a clock frequency divider.

φ1. φ2 is a clock pulse, T~ is a pit pulse,
D1 to 8 indicate 4 digit pulses, and their timing chart is
As shown in the figure.

FIG. 1 n, to n3□ are φ1. A closed loop is formed with a 32-pit dynamic shift register driven by a two-phase pulse of φ2, and the time signal is memorized as a cycle.

21. FIG. 3 shows the details of the time signal stored in this register at the time T.

Exclusive or gate EX and AND gate AN
D1 forms a half adder, and when Dl and T1, the OR gate O
A clock addition of +1 is performed through R1, OR2, and AND2.

naa is a shift register that stores a carry signal for each bit.

AND3~. ．． 0R3n34 is a circuit that outputs a carry signal and a reset signal for each digit, and the data input to 132 to n29 is either hexadecimal with 10 minute digits and 10 seconds digits, or 10 digits such as 1 minute digits and 1 second digits. The advance is detected by the timing of the digit pulses D1 to D8, and a carry signal is output to OR2 and a reset signal is output to OR4 depending on the data values input to n3□ to n29.

The reset signal sequentially resets the digits that have been over-carried by AND6.

Further, the carry signal is added to the upper digits input to n32 to n29 at the next timing.

The carry signal passes through OR2, and the reset signal passes through OR4゜AN
Sent through D6.

A decoder (2) receives a 4-bit signal from the shift register and converts it into a signal for driving the electro-optical display (2).

The output signals of the decoder are divided into two groups, parallel-in, serial-out shift registers ■, ■
sent to.

The function of these shift registers (2) and (2) is to convert the parallel signal of the decoder (2) into a temporally serial serial signal.

FIG. 4 shows one bit of the shift registers ■ and ■.

In FIG. 4, first, when the shift pulse φ2 is at the by level, the serial input SI is read into the register and output to the data output terminal DO.

At this time, the parallel input PI is the shift pulse T4. φ1
By being at a low level, reading into the register is prohibited.

Next, when the φ2 power field level is reached, reading of PI is prohibited and T4. Since φ1 is at a low level, the Do data is held by two closed-loop inverters connected to DO in the register.

In addition, the parallel human-powered PI is T4. When φ2 is at by level, it is read into the register.

At this time, φ2 is at a low level.

Next, T4. When φ2 is at a low level, reading into the PI register is prohibited, and since φ2 is at a low level, the DO data is held by two closed-loop inverters connected to the DO in the register.゜T4. Due to the series of operations of φ1, SI and PI data become D.
Shifted to O.

The outputs of the shift registers (2) and (2) alternately send forward and reverse logic signals to the drive shift registers (2) and (2) through EX3, (4).

The gate signal COM which is alternately switched is an IHz signal called out to n35, and also drives the common electrode of the display body (2).

The pulse for shifting the shift registers ■ and ■ is n36. E
This is the part φ2' of φ2 extracted by X2°AND7.

φ2. . The signals of φ2' and EX are shown in FIG.

n35 and n36 each output IHz signals having different phases, and EX2 outputs a signal that becomes bi-level for about 4 ms twice a second as shown in FIG.

The signal of EX2 outputs φ2' which is supplied to AND2.

Shift φ2'. When applied to registers 6 and 7, shift register ■.

In case (2), the transfer operation is performed for about 4 ms at the beginning of 0.5 seconds.

FIG. 5 shows one bit of ■ and ■.

In FIG. 5, the serial manual input SI is read into the register when the shift 7 pulse φ2' is at the by level.
It is output to the data output terminal DO.

Next, when φ2' is at level, reading of SI into the register is prohibited, and DO data is held by two inverters forming a closed loop connected to DO.

In this way, new SIs are shifted into the register one after another by φ2'.

Display body (2) is driven by the parallel outputs of shift registers (2) and (3).

That is, the drive signal changes every 0.5 seconds at its initial moment, ■, ■
It is written in series to , is later stored and held in a register for a long period of time, and drives ■.

In the example shown in Figure 1, the frequency of the crystal oscillator is 16.384H.
Since the digit signal is 256 Hz, the writing time is extremely short, about 4 ms, and does not cause any flickering to the eyes.

Therefore, since the writing cycle is every 0.5 seconds, the driving time after writing is 0.496 seconds, which has the effect of averaging and reducing the power consumption during writing, which consumes a relatively large amount.

This is extremely effective in terms of the construction of the wristwatch.

In the case of calculators, etc., unlike watches, the display contents change irregularly and may change quickly, so the writing cycle of display information cannot always be set to 0.5 seconds, but there is a key-in. Power consumption can be reduced by writing in response to key-in at a cycle of several Hz only at times, and writing at a longer cycle during normal times when there is no key-in.

As shown in FIG. 1, the driving signals for the direction and segment are divided into two groups and sent to the shift registers (1) and (2), respectively, but this has an advantage in the structure of the display body, as shown in FIG. 6.

That is, IC is formed on a substrate having segment electrodes,
By arranging and connecting wires, the number of connections between the display panel and the external drive circuit can be significantly reduced, making it easier to incorporate the display panel into electronic equipment or to replace the display panel.

As described above, the present invention divides the segments of the display body into a plurality of groups and drives each group by a different shift register, thereby shortening the transfer time of the shift register and achieving a good display without flickering. can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an electronic timepiece according to the present invention. ■ is a crystal oscillator, and ■ is a pulse former that also serves as a frequency divider. ■ is a decoder, ■, ■ are parallel in-serial out registers, ■, ■ are drive shift registers, ■ is a display, n1 to 36 are two-phase dynamic shift registers, AND, ~7 are AND gates, OR1-4 are or gates, EX1-4 are exclusive or gates. FIG. 2 is a time chart showing the waveforms of each part of FIG. 1 (2) and (2). Figure 3 shows shift register 0 at t=D1, 11 o'clock.
The contents stored in 1 to n32 are shown. 4 and 5 show the shift register (■) in FIG. 1. These are specific examples of ■, ■, and ■. SI indicates serial input, PI indicates parallel input, and DO indicates data output terminal. FIG. 6 is a plan view of a substrate (2) having segment electrodes of a display body. ■, ■ are the IC chips in Figure 1 ■, ■, I)-I
N is a data input terminal. Figure 7 shows φ2. 3 is a timing chart showing waveforms of φ2' and EXl.

Claims (1)

[Claims] 1. In a liquid crystal display device that has a plurality of segment electrodes on the same substrate and displays a series of numbers, the segment electrodes are classified into at least two groups, and the segment electrodes are classified into at least two groups, each of which corresponds to a corresponding shift register. A liquid crystal display device characterized in that drive signals supplied to the segment electrodes are supplied as temporally serial serial signals, and the serial signals are inverted at regular intervals together with signals supplied to counter electrodes of the liquid crystal display device. Display device.