JPS5826536Y2 - Stacked semiconductor device - Google Patents
Stacked semiconductor deviceInfo
- Publication number
- JPS5826536Y2 JPS5826536Y2 JP1977064248U JP6424877U JPS5826536Y2 JP S5826536 Y2 JPS5826536 Y2 JP S5826536Y2 JP 1977064248 U JP1977064248 U JP 1977064248U JP 6424877 U JP6424877 U JP 6424877U JP S5826536 Y2 JPS5826536 Y2 JP S5826536Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- external terminals
- semiconductor
- external
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は積層型半導体装置に間し、特に実装密度が高く
、かつ外部端子間の間隔を広くしてワイヤボンディング
を行ないやすくした積層型半導体装置を容易かつ高歩留
りに得ようとするものである。[Detailed Description of the Invention] The present invention is directed to a stacked semiconductor device, in particular, which has a high packaging density and wide spacing between external terminals to facilitate wire bonding. That's what you're trying to get.
従来の積層型半導体装置は、複数個の半導体素子を相互
配線してこれを樹脂封止したものが提案されていた。Conventional stacked semiconductor devices have been proposed in which a plurality of semiconductor elements are interconnected and sealed with resin.
しかし、この従来の積層型半導体装置では、半導体素子
の集積度が向上するにつれて外部端子数も増加するため
、装置全体を大きくするか、または、外部端子間の間隔
を狭くしなければならなかった。However, in conventional stacked semiconductor devices, the number of external terminals increases as the degree of integration of semiconductor elements improves, so the overall size of the device must be increased or the spacing between external terminals must be narrowed. .
装置全体が大きいと、この装置を電子機器等に装填され
た時に実装密度が低下するという欠点があり、また、外
部端子間の間隔が狭いと、ワイヤボンディングが行ない
にくくなるとともに外部端子間の静電容量が大きくなり
、特に高周波ICなどにおいては大きな問題となる。If the entire device is large, there is a disadvantage that the packaging density will be reduced when this device is loaded into electronic equipment, etc. Also, if the spacing between external terminals is narrow, it will be difficult to perform wire bonding and static noise between external terminals will be reduced. The capacitance increases, which is a big problem especially in high frequency ICs.
本考案は上記従来の集積型半導体装置の欠点を解消する
ものであり、以下に本考案の実施例について第1〜3図
とともに説明する。The present invention eliminates the drawbacks of the conventional integrated semiconductor device described above, and embodiments of the present invention will be described below with reference to FIGS. 1 to 3.
第1図イは本考案の一実施例を示す積層型半導体装置の
平面図であり、第1図口は同装置の断面図である。FIG. 1A is a plan view of a stacked semiconductor device showing an embodiment of the present invention, and FIG. 1A is a sectional view of the same device.
この第1図イ9口において、1,2は外部端子3,4が
接続された半導体素子であり、それぞれリードフレーム
5,6に設置されており、このリードフレーム5,6と
ともに外部成形樹脂部7,8によりそれぞれ樹脂封止さ
れ、検査、例えばDC検査、AC検査(ゲイン、高周波
特性、下電流特性)、あるいはスクリーニング検査によ
り、それぞれが良品と判定された半導体装置9,10を
構成している。In FIG. 1, A9, 1 and 2 are semiconductor elements to which external terminals 3 and 4 are connected, and are installed on lead frames 5 and 6, respectively, and together with the lead frames 5 and 6, external molded resin parts are attached. 7 and 8 constitute semiconductor devices 9 and 10, each of which is sealed with resin and determined to be non-defective by inspection, for example, DC inspection, AC inspection (gain, high frequency characteristics, lower current characteristics), or screening inspection. There is.
なお外部成形樹脂部7,8は半導体素子1,2側は厚く
形成されており、リードフレーム5,6側は非常に薄く
、例えば0.5mm以下に形成されるか、または全く形
成されていなくても良い。Note that the external molded resin parts 7 and 8 are formed thickly on the semiconductor elements 1 and 2 side, and are very thin on the lead frame 5 and 6 side, for example, 0.5 mm or less, or are not formed at all. It's okay.
11は樹脂含浸繊維材接着シ−トであり、この樹脂含浸
繊維材接着シート11を介して、前記半導体装置9,1
0のリードフレーム5.6側の表面が対向して接着され
ている。Reference numeral 11 denotes a resin-impregnated fiber material adhesive sheet, and the semiconductor devices 9 and 1 are
The surfaces of lead frames 5 and 6 on the lead frames 5 and 6 are bonded to each other so as to face each other.
そして、半導体装置9の外部端子3と半導体装置10の
外部端子4とは互いに接触することを防止するために位
置をずらして配置されている。The external terminals 3 of the semiconductor device 9 and the external terminals 4 of the semiconductor device 10 are arranged with their positions shifted to prevent them from coming into contact with each other.
上記構成から明らかなように、機械的強度の大きい樹脂
含浸繊維材接着シート11を介して半導体装置9,10
が対向して接着されているので、各半導体装置9,10
のリードフレーム5,6側の外部成形樹脂部7,8は非
常に薄く形成されても良く、また、全く形成されていな
くても良い。As is clear from the above configuration, the semiconductor devices 9 and 10 are
are bonded facing each other, so each semiconductor device 9, 10
The externally molded resin parts 7 and 8 on the lead frames 5 and 6 may be formed very thinly, or may not be formed at all.
またこのことにより、一方の半導体装置9の外部端子3
と、他方の半導体装置10の外部端子4とが近接し、時
には接触してしまうこともあるが、これらの外部端子3
.4を互にずらして配置しであるので、各外部端子3,
4間の間隔が広く、ワイヤボンディングが行ないやすく
なるとともに外部端子3,4間の静電容量が小さくなる
。Moreover, this allows the external terminal 3 of one semiconductor device 9 to
and the external terminal 4 of the other semiconductor device 10 are close to each other, and sometimes come into contact with each other.
.. 4 are arranged offset from each other, so each external terminal 3,
The distance between the external terminals 3 and 4 is wide, making wire bonding easier and reducing the capacitance between the external terminals 3 and 4.
また半導体装置9,10は別々に樹脂封止を行なったあ
と検査を行ない良品と判定されたものであるため、二個
を組み合わせても組合わせたものが不良となることがな
い。Furthermore, since the semiconductor devices 9 and 10 are individually resin-sealed and then inspected and determined to be good, even if the two are combined, the combination will not be defective.
なお、外部端子間の静電容量が大きくても問題とならな
い場合には第2図に示すように、外部端子15のうちの
外部成形樹脂部16内に位置する部分の一部17を大き
く、例えば広くしたり、また、この外部端子15の一部
17内に貫通孔18を設け、この貫通孔18内に外部成
形樹脂を充填したりすることにより、外部端子の引き抜
き強度を大きくすると良い。In addition, if the capacitance between the external terminals is large and does not cause a problem, as shown in FIG. For example, it is preferable to increase the pull-out strength of the external terminal by widening it or by providing a through hole 18 in a part 17 of the external terminal 15 and filling the through hole 18 with external molding resin.
次に、本考案の他の実施例を示す積層型半導体装置の平
面図を第3図イに示し、同断面図を第3図口に示す。Next, a plan view of a stacked semiconductor device showing another embodiment of the present invention is shown in FIG. 3A, and a sectional view thereof is shown in FIG.
この第3図イ9口において、前記実施例を示す第1図と
同一構成物に対しては同一番号が附しである。In FIG. 3A, the same components as those in FIG. 1 showing the above-mentioned embodiment are given the same numbers.
そして、一方の外部成形樹脂部7により樹脂封止された
半導体素子1に接続された外部端子21と、他方の外部
成形樹脂部8により樹脂封止された半導体素子2に接続
された外部端子22とは互いに垂直に交差するように配
置されている。An external terminal 21 connected to the semiconductor element 1 resin-sealed by one external molded resin part 7 and an external terminal 22 connected to the semiconductor element 2 resin-sealed by the other external molded resin part 8. are arranged so as to intersect perpendicularly to each other.
すなわち、一方の外部端子21は一方向、またはその反
対方向に導出して配置されており、他方の外部端子22
は前記外部端子21と垂直に交差するように配置されて
いる。That is, one external terminal 21 is arranged leading out in one direction or the opposite direction, and the other external terminal 22
are arranged to perpendicularly intersect with the external terminal 21.
このことにより、一方の外部端子21と他方の外部端子
22とが近接することもなく、また、接触することもな
い。As a result, one external terminal 21 and the other external terminal 22 do not come close to each other or come into contact with each other.
なお、上記各実施例において、1個の積層型半導体装置
には、2個の半導体素子が埋設されている場合、すなわ
ち−個の半導体素子を設けた半導体装置を2個、樹脂含
浸繊維材接着シートを介して接着した場合について説明
したが、各半導体装置には複数の半導体素子が設けられ
ていても良い。In each of the above embodiments, when two semiconductor elements are embedded in one stacked semiconductor device, that is, two semiconductor devices each having - semiconductor elements are bonded to a resin-impregnated fiber material. Although the case where the semiconductor elements are bonded via a sheet has been described, each semiconductor device may be provided with a plurality of semiconductor elements.
以上の説明から明らかなように本考案によれば、実装密
度が高く、かつ、外部端子間の間隔を広くしてワイヤボ
ンディングを行ないやすくした積層型半導体装置を得る
ことができるとともに、個々に検査が終了した良品の半
導体装置を組合わせて高密度な装置を歩留り良く得るこ
とができる。As is clear from the above description, according to the present invention, it is possible to obtain a stacked semiconductor device that has a high packaging density, widens the distance between external terminals and facilitates wire bonding, and also allows for individual inspection. A high-density device can be obtained at a high yield by combining good quality semiconductor devices that have been completely processed.
第1図イは本考案の一実施例を示す積層型半導体装置の
平面図、第1図口は同断面図、第2図は本考案の他の実
施例を示す積層型半導体装置の一部平面図、第3図イは
本考案のさらに他の実施例を示す積層型半導体装置の平
面図、第3図口は同断面図である。
1.2・・・・・・半導体素子、3,4,15,21.
22・・・・・・外部端子、5,6・・・・・・リード
フレーム、7,8.16・・・・・・外部成形樹脂部、
9,10・・・・・・半導体装置、11・・・・・・樹
脂含浸繊維材接着シート。Fig. 1A is a plan view of a stacked semiconductor device showing one embodiment of the present invention, the opening in Fig. 1 is a sectional view of the same, and Fig. 2 is a part of a stacked semiconductor device showing another embodiment of the invention. 3A is a plan view of a stacked semiconductor device showing still another embodiment of the present invention, and FIG. 3A is a sectional view of the same. 1.2... Semiconductor element, 3, 4, 15, 21.
22... External terminal, 5, 6... Lead frame, 7, 8.16... External molded resin part,
9, 10...Semiconductor device, 11...Resin-impregnated fiber material adhesive sheet.
Claims (3)
およびこの半導体素子を設置したリードフレームを外部
成形樹脂部により樹脂封止した別体の半導体装置を2個
備え、樹脂含浸繊維材接着シートを介して前記2個の半
導体装置を、前記リードフレームの前記半導体素子を載
置していない側の主面が互いに対向して接着してなるこ
とを特徴とする積層型半導体装置。(1) Equipped with two separate semiconductor devices in which the entire semiconductor element electrically connected to external terminals and the lead frame on which the semiconductor element is installed are resin-sealed with an externally molded resin part, and resin-impregnated fiber material is bonded. A stacked semiconductor device, characterized in that the two semiconductor devices are bonded to each other via a sheet, with main surfaces of the lead frame on the side on which the semiconductor element is not placed facing each other.
の半導体装置の外部端子が配置されていることを特徴と
する実用新案登録請求の範囲第1項に記載の積層型半導
体装置。(2) The stacked semiconductor device according to claim 1, wherein an external terminal of one semiconductor device is arranged between adjacent external terminals of the other semiconductor device.
面から導出して配置されており、この外部端子に垂直に
交差して他方の半導体装置の外部端子が配置されている
ことを特徴とする実用新案登録請求の範囲第1項記載の
積層型半導体装置。(3) The external terminals of one semiconductor device are arranged extending out from two opposing side surfaces, and the external terminals of the other semiconductor device are arranged perpendicularly crossing these external terminals. A stacked semiconductor device according to claim 1 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977064248U JPS5826536Y2 (en) | 1977-05-18 | 1977-05-18 | Stacked semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977064248U JPS5826536Y2 (en) | 1977-05-18 | 1977-05-18 | Stacked semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53159273U JPS53159273U (en) | 1978-12-13 |
| JPS5826536Y2 true JPS5826536Y2 (en) | 1983-06-08 |
Family
ID=28968194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1977064248U Expired JPS5826536Y2 (en) | 1977-05-18 | 1977-05-18 | Stacked semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826536Y2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5036281Y2 (en) * | 1971-07-26 | 1975-10-22 | ||
| JPS589585B2 (en) * | 1974-10-04 | 1983-02-22 | 日本電気株式会社 | Dense hinge lead frame |
-
1977
- 1977-05-18 JP JP1977064248U patent/JPS5826536Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53159273U (en) | 1978-12-13 |
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