JPS5832435A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5832435A
JPS5832435A JP56130549A JP13054981A JPS5832435A JP S5832435 A JPS5832435 A JP S5832435A JP 56130549 A JP56130549 A JP 56130549A JP 13054981 A JP13054981 A JP 13054981A JP S5832435 A JPS5832435 A JP S5832435A
Authority
JP
Japan
Prior art keywords
case
cap
ring
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56130549A
Other languages
Japanese (ja)
Inventor
Noboru Deguchi
出口　登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56130549A priority Critical patent/JPS5832435A/en
Publication of JPS5832435A publication Critical patent/JPS5832435A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires

Landscapes

  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PURPOSE:To prevent a melted alloy from spraying in a semiconductor chip contained package case, when hermetic sealing the case and its cap, by inserting a metal ring between them and sealing the outer side of the ring with an Au-Sn eutectic alloy. CONSTITUTION:When hermetic sealing a case 1 containing a semiconductor chip 3 and a cap 2 by means of thermo compression bonding an Au metal ring 4 is inserted between metallized layers 1a, 2a at the contacting surface of the case and the cap. Then, hermetic sealing is made by applying an Au-Sn eutectic alloy solder 4 to the outer side of the ring 4. Since the solder is applied only to the ring outer side and not to the metallized layers, melted alloy spraying within the package case can be eliminated.

Description

【発明の詳細な説明】 本発明は、パッケージケース内に半導体チップを収容し
キャップをかぶせて気密封着し死生導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a life-death conductor device in which a semiconductor chip is housed in a package case and hermetically sealed by covering the semiconductor chip with a cap.

半導体装置において、パッケージはその中に収納される
半導体チップを外気から完全に遮断して湿気や塵介の侵
入を防ぎ侠置Ｏｑ＃性劣化を防止することができるもの
でなければならない。このような要求を満足するものと
して、第１図に示すように、キャップ２の周辺に形成さ
れたメタライズ層２ｍとパッケージケース（以下単にケ
ースという）１上に形成されたメタライズ層１１１０間
に。In a semiconductor device, a package must be capable of completely shielding a semiconductor chip housed therein from the outside air, preventing the intrusion of moisture and dust, and preventing deterioration of air quality during storage. As shown in FIG. 1, a metallized layer 1110 is formed between the metallized layer 2m formed around the cap 2 and the metallized layer 1110 formed on the package case (hereinafter simply referred to as case) 1 to satisfy such requirements.

金スズ共晶半田４ｔ−介してろう付けすることによりて
、半導体装ツブ３の収納されたパッケージ内部を気密封
止する。この様にして、外部侵入物による半導体装置の
特性劣化の防止をはかり、装置の信頼性を高める様にし
ている。The inside of the package in which the semiconductor chip 3 is housed is hermetically sealed by brazing through the gold-tin eutectic solder 4t. In this way, deterioration of the characteristics of the semiconductor device due to external invaders is prevented, and the reliability of the device is increased.

しかしながら、この様な従来の半導体装置では。However, in such conventional semiconductor devices.

ケース１上に形成されたメタライズ層１ｍとキャップ２
０周辺に形成されたメタライズ層２暑との間に、金スズ
共晶半田４を置いて封着する構造になっているため、金
スズ共晶半田４が溶ける際に。1 m of metallized layer formed on case 1 and cap 2
Since the gold-tin eutectic solder 4 is placed and sealed between the metallized layer 2 and the metallized layer 2 formed around the 0, when the gold-tin eutectic solder 4 melts.

その溶融飛沫がケース内に飛びはねることが多く。The molten droplets often splash into the case.

その結果、半導体チップ３の上、及びケース内に前記飛
沫が付着することとなシ、特性劣化を招き。As a result, the droplets adhere to the top of the semiconductor chip 3 and inside the case, leading to deterioration of characteristics.

半導体装置の信頼性および寿命を劣化させるという問題
を生じている。This poses a problem of deteriorating the reliability and lifespan of semiconductor devices.

本発明の目的は、上述した従来の半導体装置の　２− 不具合を解消して、信頼性の向上された半導体装置を提
供するＫｔｈる。An object of the present invention is to solve the above-mentioned problems of the conventional semiconductor device and provide a semiconductor device with improved reliability.

本発明の半導体装置は、半導体チップが収容されたケー
スとケースにかぶせて気密封着するキヤ、プとの間に金
属リングをはさみ、この金属リングの外側を金スズ共晶
合金で封着した構成を有する。In the semiconductor device of the present invention, a metal ring is sandwiched between a case in which a semiconductor chip is housed and a cap that is placed over the case for airtight sealing, and the outside of this metal ring is sealed with a gold-tin eutectic alloy. It has a configuration.

つぎに本発明を実施例に゛より説明する。第２図は本発
明の一実施例を示す半導体装置の断面図である。第２図
において、ケース１とキャップ２との間に金属リング（
本発明の場合は金リング）５をはさみ、熱圧着法によっ
てケース１とキャップ２とをくっつける。次に、その外
側を金スズ共晶半田４によって封着する。Next, the present invention will be explained based on examples. FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention. In Figure 2, a metal ring (
In the case of the present invention, the case 1 and the cap 2 are attached to each other by a thermocompression method using a gold ring (5) in between. Next, the outside thereof is sealed with gold-tin eutectic solder 4.

このようにして作られた本発明の半導体装置では、キャ
ップをケースに封着する場合、金スズ共晶半田が溶ける
際に生じる半田飛沫は、ケース３とキャップ１との間に
はさんで金属リング５によって防止されケース内部に入
ることはない。In the semiconductor device of the present invention manufactured in this manner, when the cap is sealed to the case, the solder droplets generated when the gold-tin eutectic solder melts are removed from the metal sandwiched between the case 3 and the cap 1. It is prevented by the ring 5 from entering the inside of the case.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の断面図、第２図は本発明の
一実施例の断面図である。FIG. 1 is a sectional view of a conventional semiconductor device, and FIG. 2 is a sectional view of an embodiment of the present invention.

Claims (1)

【特許請求の範囲】 半導体チップを収容したパッケージケースにキャップ【
かぶせ気密封着してなる半導体装置において、前記ケー
スとキャップとの間に金属リングをはさみ、＃金属リン
グの外側を金スズ共晶合金で封着し九ことｔ４！微とす
る半導体装置。[Claims] A cap [
In a semiconductor device formed by overlapping and airtight sealing, a metal ring is sandwiched between the case and the cap, and the outside of the metal ring is sealed with a gold-tin eutectic alloy. Micro-semiconductor devices.
JP56130549A 1981-08-20 1981-08-20 Semiconductor device Pending JPS5832435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56130549A JPS5832435A (en) 1981-08-20 1981-08-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56130549A JPS5832435A (en) 1981-08-20 1981-08-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5832435A true JPS5832435A (en) 1983-02-25

Family

ID=15036930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56130549A Pending JPS5832435A (en) 1981-08-20 1981-08-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5832435A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130057A (en) * 1984-07-20 1986-02-12 Mitsubishi Electric Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5680148A (en) * 1979-12-06 1981-07-01 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5680148A (en) * 1979-12-06 1981-07-01 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130057A (en) * 1984-07-20 1986-02-12 Mitsubishi Electric Corp Semiconductor device

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