JPS5833364A - Vertical synchronization signal separation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for separating a vertical synchronization signal from a video synchronization signal.

The conventional vertical signal synchronization circuit consists of an integral circuit +
1) and a waveform shaping circuit (2).
(Figure 92(a)) is input to the integrating circuit (1) and integrated,
The waveform shaping circuit (2) shapes the integral waveform [Fig. 2 (C)] obtained at the output, and outputs a vertical synchronization signal Vs (Vs) representing the period from the equalization pulse section (3) to the vertical synchronization section (4). Figure 2(b)) is obtained. However, this separation circuit is very weak against noise (accurate separation cannot be performed) because the integration circuit (1) also integrates the noise contained in the video synchronization signal V at the same time.Furthermore, the waveform shaping circuit (2) Because shaping is performed using a threshold, the exact phase relative to the video synchronization signal cannot be determined.

Therefore, this method was developed to avoid the above drawbacks.It is digitally processed and has high reliability against noise, and it is also possible to maintain a constant phase with respect to the synchronization signal number ζ. Provide what you can. An embodiment of the present invention will be described below with reference to FIGS. 8 and 4.

(5) is the first D-type flip-flop, and the clock (CK) is supplied with the video synchronization signal V via the inverter (6).
C1144 (a)
V (Figure 4 (b)) # (input, data input (g)
is connected to logic level "l". In (7), the output Q of the first D-type flip-flop +S) is at logic level 61.
This is a counter that starts counting when it flips to ``, and detects the passage of a certain period of time.It uses a signal with a higher frequency than the video synchronization signal as the clock signal (8), and here it is 100 times the video synchronization signal. The following frequencies are used, and the counter (7) has a count value Np of the clock signal (8) corresponding to a period t2, which is slightly wider than the period t1 from the falling edge to the rising edge of the video synchronizing signal. When the actual count value NR reaches NP, a reset signal (9) (FIG. 4(d),) is output to reset the first D-type flip-flop (5). .QO is the second D type flippf Ptub, @1's Dll
The output of the flip-flop t) [Fig. 4 (C)] is used as the clock input (CK), and the video synchronization signal V is input to the data input.
is connected.

With this configuration, the second D-type flip-flop Q□ samples the video synchronization signal V every time the output d of the first D-type flip-flop (5) returns from logic level "O" to "1". Then, the output Q of the D-type flip-flop a6 of @2 changes as shown in FIG. 4(e), and the vertical synchronizing signal v8 can be separated.

In the above embodiment, the counter (7) starts counting by setting the first D-type flip 70 at the falling timing of the video synchronization signal V, but this is input to the vertical synchronization signal separation circuit. The video synchronization signal V is W! Figure 44 (b
), the counter is configured to start counting at the rising edge of the video synchronization signal.

As described above, the present invention includes a counter that starts counting a clock signal at the falling edge or rising edge of an input video synchronization signal and detects the passage of a certain time; A D-type flip-flop is provided that samples the video synchronization signal each time it is detected, and in order to obtain a vertical synchronization signal separated from the D-type flip-flop output, vertical synchronization is performed using a phase difference determined by the count value of the counter from the video synchronization signal. The signals can be separated, and the only variation between vertical synchronization signal separation circuits is the variation in the clock signal. This variation will not be a problem if the clock signal frequency is set to 100 times or more the video signal frequency.

Furthermore, since sampling is done digitally, it is possible to solve the conventional noise problem, and the vertical synchronization signal can be separated with an accurate phase difference without considering variations in circuit components, temperature, and other conditions. It is something that can be done.

[Brief explanation of the drawing]

Figure 1 shows a conventional IL direct synchronization signal separation circuit, Figure 2 is a waveform diagram of the main part of Figure 1, Figure 8 and @4-Figure show an embodiment of the present invention, and Figure 8 shows the present invention. FIG. 4 is a configuration diagram of the vertical signal synchronization separation circuit according to the invention, and FIG. 4 is a waveform diagram of the main part of FIG. 8. ■...Video synchronization signal, (5)...First D-type flip-flop, (7)...-power output, (8)...Clock signal, (9)...Reset signal , 4th... 2nd
D type flip-flop. ■8... Vertical synchronization signal agent Yoshihiro Morimoto Figure 1 7 Figure 2

Claims (1)

[Claims] 1. A counter that starts counting the clock signal at the falling or rising edge of the video synchronization signal and detects the passage of a certain period of time, and a counter that samples the video synchronization signal every time the nuclear printer detects the passage of a certain period of time. 1. A vertical synchronization signal separation circuit comprising a D-type flip-flop and obtaining a vertical synchronization signal separated from the output of the D-type flip-flop.