JPS5837814A - Digital recorder and reproducer - Google Patents

Abstract

PURPOSE:To set the optimum recording level for a recorder at the dubbing side, by providing a means at the input side of a sound recording system to produce a reference signal having a level approximately equal to the maximum level of an analog signal which is delivered from a reproducing system. CONSTITUTION:A digital recorder/reproduder is provided with a recording system that supplies an analog signal to a magnetic tape after converting it into a digital signal; a reproducing system that convertes the digital signal reproduced out of the magnetic tape into the original analog signal; and a reference signal producing means 18 that is set at the input side of the recording system and produces the reference signal that can produce a level approximately equal to the maximum level of the output signal given from the reproducing system. Then the optimum recording level can be set for a tape recorder at the dubbing side in the dubbing mode and while the means 18 is selectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital recording/reproducing apparatus equipped with reference signal generating means.

Recently, in the field of audio instruments, PCM (pHl
A digital recording and reproducing system using Cods ModwlaHom technology has been developed.

Such a digital recording/reproducing system is based on the principle that during recording, an audio analog signal (V) is first converted into a digital signal and recorded on a magnetic tape, and then during playback, the digital signal reproduced from the magnetic tape is converted into an audio analog signal. This is realized by

Specifically, one audio analog signal is sampled at a certain period, so this sampled audio analog signal is one, for example, an analog signal.
The signal is quantized and encoded by a digital converter, and R-converted into a digital key code. This digital signal is subjected to processing such as addition of an additional error detection code for error correction and interleaving at the time of recording, and is then recorded on, for example, an NTSq11 quasi-television signal video tape recorder. Then, the NT8C@semi-television signal played back from this video tape recorder is demodulated, and the extracted digital data undergoes processing such as dinterleap, error detection, and error correction to restore the original audio analog. The signal is converted into an added digital signal. This digital signal is
The original audio analog signal is restored by a digital-to-analog converter that is opposite to the analog-to-digital converter described above.

This type of digital recording/playback device is conventionally known as a PCM recording/playback device, and by converting audio analog signals into digital GI and recording them, it is possible to convert analog audio signals into digital GI signals and record them. Technical Limits Associated with Tape Recorders 1 For example, the physical characteristics of the magnetic tape used as the recording medium, such as the maximum level, and the mechanical precision of each mechanical part of the tape recorder itself, which adversely affect acoustic temporality. High fidelity recording and playback can be achieved without any interference.

By the way, such a PCM recording and reproducing apparatus (that is, a digital recording and reproducing apparatus) is not provided with a means for indicating the maximum level of a signal that can be reproduced at one o'clock.

Therefore, when performing a dubbing operation from a PCM recording and playback device to an analog tape recorder such as a cassette tape recorder, the maximum level of the signal that can be recorded and played back by the above-mentioned PCM recording and playback device is not known. It has the disadvantage that it is difficult to set the level to the optimum condition.

This invention has been made in view of the above points, and is a digital recording/playback device having a digital recording system and a playback system.
By providing a middle stage of reference signal generation that can give a level approximately equivalent to the maximum level of the analog signal output from the reproduction system on the input side of the Ik-recording system, it is possible to use Rw selectively during dubbing while the reference signal is being generated. To provide an attractive digital recording playback device FIT which can set the optimum recording level of a dubbing side tape recorder.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

That is, as shown in FIG. 41, the recording input terminals INII and INR of both the left and right channels are connected to the input terminals of the amplifier II512, respectively. Each output terminal of this amplifier Ille IJ is connected to a pair of inputs of a mixing circuit @IS comprising a sample-and-hold path, through a correspondingly low-pass filter with a cut-off frequency IDK)lz, for example. Terminal C is connected.

The output terminal of this mixing circuit 15 is connected to one input terminal of a switching circuit JF via an analog-digital conversion circuit (hereinafter referred to as ADC) 16'. A reference signal is generated at the input 1 of
i! The output terminal of 1ll1818 is connected.

The output terminal of this switching circuit 17 is connected to the input terminal of the recording processing m circuit 1fl. An output terminal of this recording processing circuit 1g is connected to a video input terminal of a video tape recorder (hereinafter abbreviated as VTR) 20.

The video output terminal of this VTRI II is the playback processing circuit J.
It is connected to the input terminal of J. This reproduction processing circuit 21
The output terminal is a digital-analog conversion path (hereinafter referred to as DA
It is connected to the input terminal of the separation circuit z1 via a cable zzyh-, abbreviated as C.

This minute III&? A pair of output terminals of the l path 23 are respectively connected to respective input terminals of a low-pass filter 26°2r with a cutoff frequency of 20 KHz via an amplifier 14a215f, respectively. It is continued.

The output terminals of these low-pass filters III and 2F are:
Correspondingly, output terminals 0υTL, 0UTx l: l-contact fa
has been done.

Further, the pair of output terminals of the above-described M circuit 28 is connected to a power amplifier SO for headphone operation via muting (B) paths 211 and 19, respectively.

11 input terminals. The output terminals of these power amplifiers son;it are respectively connected correspondingly to one segment of the headphone jack 32 to which the common terminal is short-circuited.

On the other hand, the switching path (2) 17. Reference signal generation tgIj8
The output terminal of switch drive Lg1wIIJ- is commonly connected to the control input terminals of l8 and muting circuits 18 and 18 and 19, respectively. This switch drive circuit 3
One end of the switch 8 is grounded and the other end of the switch 8 is connected to the input terminal of the switch 1 .

In the PGM recording/playback device configured in this way, the switch drive circuit 33 is configured with a dattering prevention circuit, a T-type freetub flop circuit, etc.
In other words, in the normal mode), its output terminal is at a low level (hereinafter referred to as L level). In this case, the switching circuit 16 selects the output signal of Aj)C16 and supplies it to the input terminal of the modulation circuit 19. is being done. In addition to this, each muting circuit 28, 29 is
It is designed to prevent muting.

That is, 1. Two systems of audio analog signals, that is, both left and right channels, which are supplied from, for example, a microphone (not shown) and serve as recorded signals, are supplied to the input terminal of the amplifier J1.14 via the input terminals INIJ and INi correspondingly. and this audio analog signal is passed through the amplifier tt,i
For example, the cutoff frequency χ20 KH
The signals are respectively supplied to a pair of input terminals of the mixing circuit 1B via low-pass filters 13, 14 with z.

Each signal supplied to this mixing circuit 15 is alternately sampled (411 signals) and multiplexed at a predetermined period, and then supplied from the output terminal of the mixing circuit 15 to the input terminal of Ct 6. It has become. The ADcl 6 is for example a 14-pit digital signal (III
(referred to as the standardization word) is serially transferred via the switching circuit 77 and supplied to the input terminal of the recording processing circuit 19 in four wires.

Then, the recording circuit 19 contains one data group of three consecutive sampling words (six for two systems) for each system of both the left and right channels (for which two types of ridge correction codes (codes (length 14 bits) and interleave processing 'fM'lk-' for each @r word and each error correction code.
At the same time, an error detection code (code length 16 bits) for error detection is added. Furthermore, the digital data consisting of these sampled words, error correction codes, and error detection codes are processed by the recording processing (2) path 19 to 1, for example, N
The signal is superimposed on one horizontal scanning period of the TBC$ quasi-TV signal (hereinafter referred to as a video signal) and is supplied to the video input terminal of the VTRJD.

Note that the above interleaving process is performed by passing each sampling word and convergence correction code constituting the data group 1 through a plurality of delays*7 each having a different delay time, for example, so as to separate horizontal scanning periods. The weight is distributed accordingly. That is, in one horizontal scanning period of the video signal, sampling words and error correction codes of six different data groups are superimposed.

As a result, the sampling words successively outputted from the %ADO'1g are recorded at separate positions on the magnetic tape, making it possible to compensate for part errors.

In contrast to the above-mentioned audio analog signal distribution system, the video signal reproduced from the VTRJO is restored to the original audio analog signal by the reproduction system described later.

In other words, the reproduced video signal is processed by the reproduction processing NItg1
The signal is demodulated by Mxt, and the digital data described above is extracted. This digital data is subjected to dinterjeep processing, which is the opposite of the interleaving processing described above, in the reproduction processing circuit 21, such as error detection using an error detection code and error correction using a g-correction code. This is converted into consecutive sampled words and supplied to the input terminal of DAe j J as a serial digital signal.

The DACJ j converts the serial digital signal t digital-to-analog conversion (hereinafter referred to as D) output from the playback processing path 21.
/A conversion) and then supplied to the separation circuit 2S as a multiplexed analog signal.

The divided I11 circuit 2S synchronizes with the DAC 2J and separates the multi-level analog signal into two systems of audio and audio analog signals for both left and right channels, and outputs them from a pair of output terminals to the corresponding amplifiers 24. I5 and low pass filter 26. \27 to the output terminals 0LITr, , 0LITR (=).

In this way, PCM sound reproduction and PCM reproduction of two systems for both the left and right channels are performed. At this time, by connecting headphones (not shown) to the headphone jack Jz, the outputs of the two systems of the dividing circuit 21 are performed. The signals can be monitored through corresponding muting circuits N111.19 and electronic amplifiers 10.31 constituting the monitoring system.

On the other hand, the turtle switch drive circuit yzss sets the output terminal to a high level (hereinafter referred to as H level) by operating the switch 8.
Then, the switching circuit 1 rs-semi-old generation signal is driven, the muting circuit J#, 19 is driven, and the PCM recording and reproducing apparatus is changed from the normal mode to the capration mode. At this time, the reference signal generating circuit 1B outputs, for example, the maximum level at which this P'CM @ ii playback device can record and reproduce (the maximum level that can be converted by the DAC) - the amplitude I11! at the output terminal. A sine wave with χ! DA when input to each input 1 child INL, INm
A digital signal equivalent to the signal output from C16 is generated. Further, the switching circuit 17 is configured to supply the reference signal generation nN11j=0) output signal to the input terminal of the recording processing circuit 19.

Therefore, the output signal of the reference signal generation port 18 is converted into a video signal by the recording processing circuit 19 via the switching circuit tr2, and is supplied to the video input terminal of the VTR 20.

By the way, VTR! When l o is in a state other than the normal playback state, the signal l applied to the video input terminal is output as is to the video output terminal. For this reason, if v'rnz O is in a poor reproduction state, the video signal is sent to the reproduction processing circuit 1621.8 by 822a, M circuit 2g, and intensifier I@j 4 in the same way as the reproduction signal of VTRj O. a j l , C7-/(Sfilta zg,
1 output terminal 0UTb, 0 by sequentially passing through zryx
A sine wave having a level substantially equal to the maximum level that can be recorded and played back by each PCM recording and playback device is output from the UTx.

At the same time, the muting circuits za and zy are driven by the switch drive circuit SS, and the output of the yIIAtillll path 21 is output from the switch drive circuit SS. Each of them is attenuated to a predetermined level and supplied to one input of each power width transducer 30, 31.

By the way, does the above explanation work? The mixing circuit 11. is omitted from description and illustration for the sake of clarity.
ADCIg, reference signal generation circuit 19. Reproduction processing circuit 19
, 4 raw processing circuit 77° DACJ! and Separation - @ZX
are supplied with a clock signal derived from a clock signal generation circuit and a control circuit (not shown) and a control signal derived from this clock signal, respectively, and predetermined operations are performed individually in synchronization with these signals. It looks like this.

Next, the ADC7B of the device shown in FIG. 1, the switching circuit IP, the reference signal generation @H5ts, and the recorder 1! IP! 1M61# and the specific configuration of the switch drive circuit 83 using the IJI2 diagram. I will clarify.

That is, the output terminal of the mixing circuit 15 is, for example, an IC.
It is connected via a terminal IN to an input terminal INa of an ABC circuit 4g constituting the ADO 7g. This A
The Dc circuit 4o has a 14-bit output terminal DI*DI
e D, ”・, Dl, and the upper 8 bits of this output terminal are all.

D,,,-・D! is the parallel input terminal Ihl*Iglm of the first shift register 41 of parallel input serial output type.
....

The lower 6 bits of this output terminal, that is, DaeD@p, D,1 are connected to the parallel input terminals I~ of the second shift register 42 of parallel input serial output type.
``K*e...a I4 @ Correspondingly connected to ICH.

This second shift register 42 has another parallel input terminal I
s, , Ib, and the series output terminal 4 are grounded, and the series output terminal Q% is connected to the series input terminal eHII of the shift register 4 of the above ml W! It is continued. The serial output terminal Qht of the first shift register 41 is connected to the switching circuit IF
A first input terminal lζ of an AND-OR gate 43, which will be described later, is connected. 9's Andor Goo) 4J
The output terminal is, for example, an IC, and is an input terminal lNd1 of the recording processing device 144 constituting the tIi distribution recording processing circuit l#.
:fI! It is continued. The recording processing device 44 has an output terminal Ov connected to a video input terminal of the VTR 20, although not shown, via a terminal ou'rvv.

The clock input terminal WBC of the recording processing device 44 has
Although not shown, the output end of an oscillator that supplies all clock signals of, for example, 1.4 hAHz is connected via a terminal CIM. At the same time, the terminal 01N is connected to the inverter 45.
e 4 g k serially through the first, l'g2
Clock input terminals CK@ of shift registers 41 and 42 of
, CK@ are commonly connected.

Again, the output terminal of the inverter 45 is connected to the clock input terminal CK of a third shift register 47 of serial input parallel output type. A pair of serial input terminals IN1. of the shift register 4r of this w43. The first branch clock Cd of the recording processing device Jit44 is connected to IN. The third shift register 47 has eight parallel output terminals Qa sQb e-aQhw*shi-c,
The circuits Qm and Qh are connected correspondingly to a pair of inputs, 4 children, of the NAND circuit 48. This cant circuit 48
The output terminal of 4@l, the second shift register 41
．． 42 shift/load terminals 8I4, 8I.

By the way, the read-only memory (hereinafter referred to as ROM) 49, which constitutes the essential part of the reference signal generation circuit 18, has address input terminals All 6 AI, . . . , An
Color/R50 each output terminal Q o e Qs #
....

Qn and %8-bit data output terminal D
r, , Drl, . . . , Drte are parallel input terminals Ik4I &
a”, Ib4.correspondingly connected to IC4.

This fourth shift register 51 has a clock input terminal G
K is connected to the output terminal of the inverter 46, the series input terminal 81 N is grounded, and the series output terminal Qh is connected to the second input terminal 2 of the AND-OR gate IS.

In addition, each output terminal QoeQ1 of the upper 6 Pikakunta 50,
. . . eQn is covered by the corresponding inputs of the combinational circuit 52, which will be described later. The first output of this combinational circuit 52 is a turtle OR circuit 53
is sitting on one input child of . This OR circuit 5
The output terminal 3 is the reset terminal CLI of the cuff 7 5Q.
:It is connected.

The clock input terminal CK of this kakunta 50 is an exclusive phase advance circuit in which a pair of input terminals are correspondingly connected to the output terminal Q a e Q'' of the shift register 47 of LKR @3 via the inverter 54. 55.The output terminal of this exclusive Wa summation circuit 5 is s
The shift/load terminal 8I4F of the shift register 51 of ff Mt m4 is connected.

The swing f8 that controls switching between the normal mode and the calibration mode is constituted by, for example, a non-locking bush type slide, one end of which is connected to a resistor Ro'! ? The midpoint of the connection between the switch f8 and the resistor R, which is connected to the power supply Vcc through the input terminal and grounded through the other terminal, is the input terminal of the holding circuit 56, which is composed of a chattering removal circuit, a T-type flip-flop circuit, etc. connected to. The output terminal of this holding circuit 56 is:

Connected to the third input terminal of the ANDOR gate 43, and directly connected to the fourth input terminal 4J of the ANDOR gate 4J. C: Common to four children CI4 (shirt of inverted input of fourth shift register 51): Crossed. In addition, the output terminal of the start-up circuit 16 is connected to the at of a light emitting diode DL whose cathode is grounded via a resistor RtY.

Note that the inverting input of the vIM1 m second shift register 41, 42 is the cat terminal CI4. CI4 is commonly connected to an Itl# circuit (not shown) via terminals CI,'. Similarly, the third shift register 47
The reset 1 child CI4 of the inverted input is connected to the control circuit at one point via CIsyt.

As shown in FIG. 3, the ROM 49 stores digital values, that is, data corresponding to the level when time is sampled at predetermined intervals in the axial direction (C11) when the reference signal is a sine wave, for example. (:) Here, if the sampling frequency 'Ik - for example 4405611JIz is taken into account 'Jj' in the VTR 20, the above sine wave is sampled every 22.6%8.

That is, each time 1. , 1m..., ik, l2, the data corresponding to each level of the sampled sine wave ■・ , ■虱 , ..., Vk- are stored in %ROM4.
9 as described later, and the data VmsVsm corresponding to the positive and negative peaks of the sine wave (that is, the maximum amplitude) is stored in s14 so that it corresponds to the maximum level at which the ICM recording/recording/playback sound can be played. The maximum and minimum values that can be expressed in binary bits (total 01.111
．． 111.111.

Ill, and 10.000,000,000.000
),! : It's a real thing. Note that %m is m = k
/4.

The above data is input to the address input terminal A of the RUM #9. ..., ^, is stored in the storage area at address (6) specified by the input.

That is, as shown in FIG. 4, each data VOa"1m.
..., Vk are each divided into the upper 8 bits and the lower 6 bits and stored in the above 1 (OM'4j).Here, the data Vt and v' representative at time 11 are 4t and ll! DTl and the above RoM4y store the upper 8 bits of data vt at address 4.9 V4, v4,
-, , V4 are stored in the ROM 4 G note 91 in correspondence with three trends Dr6, Drl, . . . , Dry, and the lower 6 bits of theta V/,
, V4.

Vja, Vlb, Vlc, Vld (Rt)M
49CD data f output terminal Dr6, Drl,...,D
It is stored in correspondence with r@. Furthermore, if the data Vt divided and stored at addresses 4t and t+1 is supplied to the left channel Lch, it is also stored at addresses 4t+2 and 4t+3 so that it is also supplied to the right channel Rch. It has become so.

Note that the storage areas corresponding to the data output terminals 7J Dr and Dr at addresses 4t41 and 4t+3 of the ROM 4m are not used and are set to 0 in binary, that is, odd addresses. The lower two bits of the data are all 0.

Moreover, as mentioned above, the first. The 2.44th shift registers 41m, 42a, and 51 have the same configuration, so that each shift register 8I has the same configuration.
4.8 When I, , si, are at L level, each clock input terminal cKl, cK, , cK.

When rises from L level to HL/a, each parallel input terminal "l a xb, a =・g Ihl @
and Ial.

”l # ・=e Ihs and I4 a Iba e
"a Ih4 (D Ly H/l/! It is designed to be loaded into each internal storage section. In this case, each shift register 41° 41.11" CD each person's power II 9 child l
The contents loaded from hl e Ikl jhl are respectively output to the serial output terminals.

On the other hand, 1 above each shift/load terminal 8I4, 8N4゜Qh
This is what is output to.

The above-mentioned AND-OR gate 41 is composed of two AND circuits and one OR circuit, and the level of the output terminal is indicated by a variable . @l.

112.1113, - If the levels of the fourth output terminal J, J It has become. However, if the input terminal of the porridge 2 is at H level and the fourth input terminal 4 is at L level, the serial output 1 child of the first shift register 41 Qht
If the signal 814, which is supplied to the input terminal of the input terminal 44 of the above AND/Is-I/I or day) 41, is at H level, each shift register 41.41 .11 is loaded into its memory and each input terminal Ial, Im, ,
・, Ih1 and Iag @ I% m ””aIh
, and I4-"*e"m Ih+ are sequentially output from each serial output terminal every time the level of each clock input terminal rises.

Note that in the above case, each reset terminal c14. CI4° CI4 is set to i level by a control circuit (not shown).

The above Il! In the shift register 46 of No. 3, the AND of the signals supplied to a pair of input terminals IN, , IN, is sequentially shifted every time the clock input terminal rises, and each parallel output terminal Q a a Q b a ...and this and or game) 4 J Cl) 2nd and 1
! 4, the output signal of the fourth shift register 5 is supplied to the input terminal of the video signal conversion circuit 44 via the AND-OR gate 41. It is.

By the way, the combination circuit w1!51 sets the ROM 49 in advance (in case 4 is the last address of stored data), sets the output terminal YH level, and resets the counter 110f via the OR circuit 53. It has become.

Further, the recording processing device 44 has a clock input terminal WB.
The clock signal supplied to the terminal C is divided into, for example, 1/8 and outputted from the branch clock terminal Cd.

Next, P is provided with the circuit described above (and shown in FIG.
(The operation of the No. 31 return sound reproduction device will be explained with reference to the timing chart of FIG. 5.

In addition,! In diagram J5, ca) is the recording processing device 144
941 (7) Output 7J signal te'), which is the clock signal supplied to the terminal CHr,
(d), (e).

Cf), *>, (hn, υ), u), and (k) are the parallel output terminals Q of the third shift register 4r, respectively.
a"a Q b -..., is the output signal of Qh, (
m) is the output signal of the serial output terminal Qb1 of shift register 4 of Igl in normal mode, and (fl)
is exclusive I! 1 is the output signal of the logic circuit and is (0)
is the output signal of the inverter 54, and ψ2 is the output signal of the serial output terminal Q4 of the fourth shift register 51.

Further, in FIG. 5, periods T and T indicate periods during which data VA is supplied to the recording processing device 44 corresponding to, for example, the left channel Lch and the young channel Rch, and the periods "h e in) e iQtml is ROM
4 m is the address 44041◆1゜4t+2,4 respectively
This shows the period during which the data stored at t+3 is output.

In the case of calibration mode, each reset terminal CIJ1. C-
and 9-e set CL of the third shift register 47
1ll are respectively connected to terminals "1" by a control circuit (not shown).
# It is set as a level via CIg.

In other words! The shift register 41 of J3 has a clock signal inverted by the inverter 45 inputted to the clock input terminal, and (13!5)
A clock signal whose frequency has been divided by φ is supplied from the branch clock terminal Cd of the recording processing device 44 to the pair of input terminals IN& and I%. (See FIG. 5) This causes the third shift register 4r to perform a left operation every time the clock input terminal CK rises, and the outputs of the respective parallel output terminals Qb.

Qc, . . . , Qk have parallel output terminal Qa output phases of 22.5°, 45”, 67.5°, and 90°.

112.5", 135", 157.5@, delayed signals are output (Figure 5 (d) #
(e) #..., (k) ε) Therefore, %IJ3
If the parallel output terminals Qa and Qh of the shift register 47 are both at H level, the output terminal of NAND circuit 4# becomes L level (see Figure 115 (A)). Shift register 41.41 i/7 to/load register 8L
1 and 8L are at the level 0. Then, when the clock signal supplied to the terminal C1w rises, the left register f41.41 of '1sx,)sz internally loads the parallel output data of the ADC4g. At this time, the first shift register 4
1f) The data loaded from the input terminal Ih1 is output to the a-column output terminal Qhi (see FIG. 5).

Next, when one clock signal falls, the third shift register 42 performs a shift operation because the clock input terminal CKs rises, and the first... The second shift registers 41, 41- are enabled for shift operation. Hereinafter, every time the clock signal rises, 1jllll, 1jllll,
ADC loaded into second shift register 41e42
The parallel output data of the circuit 40 is Di s Di m・
・、.

In the order of D
The above serial signal is processed by N' in the recording processing device 44.
Since it is superimposed on the IFI C standard television signal, the input terminal Ikl of the second shift register 4z is
xs11m 'l is grounded and the lower 2 bits are at L level (
In other words, the process is set to 0).

Like this %IJI,! J2 shift register 41.
When the 16-pit data QhI loaded in the shift register 42 is output, both the parallel output terminals Qa and Qb of the third shift register 4r are set to H level again (Fig. 5(d)
), Oc) ), 11 at the rising edge of the next clock signal! The 111Hz shift register 4taaz has:
Each parallel output data of ADC[gl circuit o is loaded. Hereinafter, as mentioned above, each shift register '1a42
The data loaded into II! 1 shift register 410) It is output from one serial output child Qhl in synchronization with a clock signal. (See cause 5).

This means - if the previous data corresponds to, for example, the left channel of the audio analog signal, then the subsequent data corresponds to the right channel of the audio analog signal. By repeating such operations, the audio analog (stereo) signal is successively converted into a serial digital signal.

On the other hand, as described above, the output terminal of the holding circuit 59 is set to the H level, so the third and 1140 input terminals of the tortoise-and-or gate 43 are set to the H and L levels, respectively, and the first shift register The output signal of the serial output terminal Qh of 41 is the AND-OR gate 4! The signal is supplied to the input terminal of the recording processing device ff144 via I'll. This gives P(
The 'M recording apparatus is capable of so-called PC, 'M recording of audio analog signals.

By the way, normal mode and calibration mode! When the switching switch 2-8 is operated, the holding circuit 5
In 6, the internal T-type flip-flop is inverted, and the output terminal becomes Level.

As a result, the OR circuit 53 has one input terminal set to L level via the inverter 5r and the other input terminal set to L level via the combination (2) path 52, so that the reset terminal CLfL of the counter 50 The reset state aV of the counter 5d is canceled as the level.

and%! Parallel output terminal q of shift register 41 of J3
aeqh' are both set to the H level, and the shift/load trend of the fourth shift register 51 ";rl8L" is set to the L level via the exclusive OR circuit 55 (Fig. 85(d), 弽). , (see (fi))), when the clock signal rises, for example, the parallel output terminal D of the ROM 49
r6 a D's, ・=a Dr, has counter 5
Data at address 0 specified by 0 vO0, Vo@
, . . .jVoy are output, and these data are loaded into the fourth shift register 5. As a result, the data VO. loaded from the parallel output terminal Dr of RL)M4m is output to the serial output terminal Qh4 of the fourth shift register 51 (see FIG. 5).

[Since the third shift register 41 performs a shift operation at the falling edge of the next clock signal t', the shift register 51 of iJ4 has a shift load Kameko 8C at H level due to the exclusive OR (b) circuit 5s. It is said that J Figure 5 (
') e O') a (E) Reference n, so every time the clock signal rises below 1, the fourth shift register 51 outputs -R.
Each parallel output terminal Dr@ of OM4M.

Data loaded from D r@ * ”' e D 'l? Vo6, Vo, *...evOql' Output T from the serial output terminal Qka as a serial digital signal
(See Figures # & 5).

Further, if the clock signal falls while the fourth shift register 51 is outputting data VO7v loaded from the parallel output terminal Drv of the JM 49, the shift register of nest 3 performs the shift operation 7 and parallel Output terminal Q a ,
Both Q and h are set to L level and sent to 1! through the exclusive OR circuit 65! ! 4 shift register ll0J shift/load terminal 8Lh'18 and -L level (Fig. 5(d)
, (&), (n)). Exclusive with this! 11 The output of the sum circuit 55 is supplied to the clock input terminal CK of the counter 5Q via the inverter 54 (fifth
11 (0)), as a result, the counter 50 increments by its content Yl at the rising edge of its Glock input terminal CK, and RUM49 increases its parallel output terminals Dro, Dr@
,..., for example, the data at address 1 Vow *■
O* e""*VO'Y is output. Each data VO torture, v
b, . As a result, the parallel output terminal Da of the ADc circuit 4° is
,..., data corresponding to D16 is output from the shift register 51 of IFg4. below)? OM
j The contents of each address of 9! ! The counter 5o is updated every time the signal is output from the shift register i4, and the same operation is repeated (see FIG. 5).

For example, if the contents at addresses 0 and 1 of ROM 49 are data corresponding to the left channel of the reference signal, the contents stored at addresses 2 and 3 are data corresponding to 6 pairs of the right channel of the reference signal, respectively. This is similar to addresses O and 1. Thereafter, data corresponding to the left and right channels of the reference signal are alternately stored as one set of storage areas each having two addresses in 0. This allows the left and right i4 Qi? A serial digital signal corresponding to the reference signal of the channel can be generated, and the contents of the counter 50 are stored in the ROM.
49 (f'-ta for iJ4nlNM, QJ5) When the address matches the address next to the last stored address, the 1st combination circuit 52 instantaneously sets its output terminal to H level and outputs the counter 50 via the OR (ro) path 6St. In this way, the contents of R(JM 49) are again output from the serial output terminal Qh of the fourth shift register 51.

Since the output terminal of the holding circuit 56 is at H level, the serial digital signal is inputted to the input terminal of the recording processing device 44 via the AND-OR gate 43.

Therefore, the VTRJ of the Pα recording/playback device.

is designed to output the human input signal directly from the video output terminal in any state other than its playback state.For this reason,
The video signal on which the digital signal corresponding to the reference signal is superimposed is demodulated by the reproduction processing circuit 2), and the digital signal of the axis tree word that is output is υAC as described above.
1giji'5JJ.

By passing through the separation circuit 2ie amplifiers i4 and 25 and the low-pass filter 26.2r, etc., the output terminals 0IJT L and Uυ'rR are converted into PCM recording and analog reference signals for both left and right channels. They will be output at the same time.

As a result, when dubbing from the Mosquito PCM Q sound reproduction device to an analog tape recorder such as a kayak table recorder, the optimum playback level of the tape recorder for dubbing is e'ii! yie can be done easily.

In addition, the output trend of the recording processing circuit 1G and the reproduction processing circuit 2
If a switch qsmv is provided on each input terminal side of 1, so that other video tape recorders (VTRs) can be connected, even if multiple VTRIs are used, a video signal with a signal sound superimposed on the above-mentioned reference signal can be recorded. be able to.

In addition, by using such a reference signal generating means, it is possible to check the basic operation of the recording and reproducing system, which is extremely convenient.

The other parallel output terminal Qb of the third shift register 47 shown in FIG.

QcaQdeQ@, Qr *Qg output is 1j! in order to synthesize other control signals T! The detailed explanation will be omitted.F: By operating the switch 8 again, the output terminal of the holding circuit 56 is set to the L level, and the current PCM recording/playback device returns to normal audio. This allows the signal to be recorded.

Incidentally, in the above case, the reference signal is generated digitally, but a similar signal can also be generated analogously.

That is, as shown in Figure %'#46, the operational term @6U of the wire 1 and the gruel 2 that constitute the analog oscillator.

61 are connected to a resistor R1 (1 and a conductor fCI) and a resistor R11 and a conductor fcII to form a well-known integrator.The output terminal of the first operational amplifier 6Q is connected to the second operational amplifier 6Q. It is connected to the inverting input terminal (-) of the amplifier 6) via the resistor R11, and is also connected to the other end of the variable resistor VR, one end of which is grounded, via the resistor R11'Ik-. The output terminal of the second operational amplifier fit is connected to the first operational amplifier through a resistor R*s'.
It is connected to the non-inverting input terminal (+) of the operational amplifier 61. This IJ! The non-inverting input terminal (+) of the first operational amplifier 60 is connected to the other end of the capacitor Cox to which - is grounded, and is grounded in an alternating current manner. There is also a resistive island that serves as the input end of the above integrator. 1, one end of which is grounded.

In addition, the above 112 operational amplifiers 6 have one output connected to the voltage [Vcc and a plurality of resistors R connected in series between Vcc and Vcc.
No. 1 e gss + e'lts # R11 of Rst
It is connected to the connection midpoint of and Lm. The inverting input terminal of the second operational amplifier 61 also has a cathode connected to the resistor R.
11ksR11 M! Diode D connected to the midpoint of the connection
Mf on the anode of s! At the same time, the anode is connected to the resistor R1@sR1? A diode D! is fitted at the midpoint of the connection. Cathode C: Connected.

In other words, these diodes D1, D, and the resistance R
t * # Rts * R 綽・Rtt and '? ! r
The power supplies Vcc and Vee' are so-called clipper li
mMY configuration, which limits the voltage at the inverting input terminal (-) of the second operational amplifier 61 to within a predetermined level range;
The stabilization of the oscillation output is as follows.

In the analog oscillator configured in this way, the movable section of the variable resistor VR is commonly connected to the input terminals x, yl of the analog switch circuit 62, which will be described later, and is used to control the oscillation of the analog oscillation circuit. The output χ is supplied to each input terminal XI, Y of the analog switch circuit 62 concerned.

This analog switch circuit 62 also has input terminals X, .
Y, and switching output terminals Xc and Yc, and three control input terminals A and B.

It is controlled by C. In other words.

Each control input terminal A, B, and C are H and H, respectively.

If the signal is at L level, the signals supplied to each input terminal 'X, Y, are correspondingly output to switching output terminal XcmYc, and each control input terminal A, B, C is set to L level, respectively. If so, the number 91 supplied to each input terminal X, Y, is outputted to the switching output terminals Xc, Yc correspondingly.

Input terminal X of the analog switch circuit 62.

Y, respectively, the - end is grounded and the other end is the input 1 child I.
Variable resistors VR, which are connected correspondingly to NL and INR,
It is correspondingly connected to the movable section of VR. Moreover, the switching output terminal XC of this analog switch circuit 62,
YC is correspondingly connected to the input terminal of each of the low-pass filters via the amplifiers 11.12f.

By the way, in the analog switch circuit 62, the control input terminals A and B are commonly connected to the output terminal of the holding circuit 61 forming the switch drive circuit say*I! IJ control input terminal C is grounded. This hold@path 63 is similar to the hold circuit 56 in the second garden, and its input terminals are connected in series to the 111 source -Vcc and il'm1iIO as shown in the figure, and the normal mode and calibration morton. It is connected to the midpoint of the connection with one end of the switching switch 8, and is also connected via a resistor R1 to the anode of a light emitting diode DL whose output terminal is grounded.

Although not shown, the output terminal of the 1MJ ADC 76 is directly connected to the input terminal of the recording processing 191w119.

That is, in the PCM recording and reproducing apparatus configured as described above, by operating the switch 8o2 to set the holding circuit 63 output terminal QH level, the output of the analog oscillation circuit (1) and It is commonly input to the input terminals of amplifiers 7J' and 72. However, in this case, the variable resistor V R#';! %
It is assumed that R4 is adjusted so that the maximum amplitude of the output stop signal of the analog oscillation circuit matches the maximum level at which the recording/playback device can record and play back P(,'M) at the input terminal of each amplifier. It is possible to obtain the same effect as in the previous embodiment in which the entire reference signal generation circuit constructed using the above-mentioned R(JMQ) is used.

In addition%! The same parts as those in Figure J1 are given the same reference numerals and their explanations will be omitted.

Furthermore, the reference signal having the maximum level of vibration @Y at which the PCM recording and playback device records may be a square wave, a triangular wave, etc., and a frequency that provides a phase difference between the left and right channels. may be made different.

As mentioned above, when a digital or LC recording/playback device is used, reference No. 16 is generated on the digital signal recording input side of the digital recording/playback device. The provision of means is a feature of the present invention.

Next, the muting circuits 78 and 29 will be explained.

In other words, as shown in Figure 187, '@1 figure is not shown in order to make the explanation easier to understand, but the previous part 1lII
I@path 2 J OJ 1 pair of outputs are respectively connected to the other ends of variable resistors VR, , VR, whose respective terminals are grounded. Each movable section of the stiff variable resistors VR1 and VR, is correspondingly connected to each input terminal of the amplifiers 14 and 1B, and the resistor ζ recondenser f-
A headphone power amplifier J (7
゜31'111- are connected to the non-inverting input terminals IN+INII of the differential amplifier rye;tt. The output terminals of these differential amplifiers to, ri are:
Resistors Rts and Rm for protecting the headphones, respectively.
It is connected to a pair of sections of the headphone jack 32 via the headphone jack 32. Note that the resistance R1,.

R,- and R, , R1 are the differential amplifiers 6ro, ii
is a resistor that determines the feedback constant of capacitors C, , C
□ is a capacitor for preventing oscillation.

In addition, the midpoint of connection between resistor "11 and content fC1l and the midpoint of connection between resistor R11 and content fC■ are connected to the respective collectors of N-compatible transistors Tr@ and Tr via resistors R*5-Rlst', respectively. These transistors T r, are correspondingly connected to .

Each emitter of the Tr snow is grounded, and each base is connected to the output terminal of the holding path 56 shown at I'j21Q via a resistor RsxaRs*'l. Note that the same subdivisions as in Figures 41 and 1I'$2 are designated by the same reference numerals, and their explanations will be omitted.

Muting circuits II and III configured in this way
Since the transistor TrN is in the off state in the normal state, the variable resistors VR, VM.

Minutes extracted through II! Each input terminal of the differential amplifier 717 and 71 is connected without attenuating the output signal of the circuit 23.
+IN, which is supplied correspondingly to i.

On the other hand, in one oscillation mode, the muting circuit 18.2
9 is a transistor 9. Since Tr and Try are in a conductive state, the extracted output signal of the distribution circuit 23 is connected to a resistor R1.
11"l and Rj M r R1. The attenuation is reduced by the amount determined by the respective constants and is correspondingly supplied to the input terminals of the differential amplifier 7 (7, 77, IN□). There is.

As a result, the maximum level reference signal is not directly input to the headphones, thereby preventing injury to the user's ears. (recording/playback device).

In addition, in the above PCM II sound playback device, VTR*
It was designed to be integrated with the other parts of the Pcu sickle sound reproduction device, but these parts are separated from each other. M 7" o yaf f 8 yah ÷ Pα recording and reproducing device! It may be configured as follows.

Other various modifications and applications are the gist of this invention! It goes without saying that this is possible as long as it does not deviate.

As described above, according to the present invention, in a digital recording/playback apparatus having a recording system and a playback system, a reference signal having a level substantially equivalent to the maximum level of an analog signal output from the playback system can be provided. By providing the signal generation means at the input of the recording system, the reference signal generation means can be selectively used and the optimal recording level of the dubbing side tape recorder can be set during dubbing. can be provided.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing one embodiment of the digital recording/reproducing device according to the present invention, and Fig. 1182 is an example of the appearance of the part shown in Fig. 1!
The circuit connection diagram shown in Figure 3 and IJ! FIG. 4 is a diagram used to explain the data Va stored in the read-only memory in FIG. 2, and shows the port connections shown in the fifth solid example i. 1l-r-12,24,25...increase'lim%ts
-14,2g, 21...Lopanefil y, ts・
...Mixed Ir? l path, 16...Analog-to-digital conversion-path (ADC), 1? -・Switching circuit, 1B... Reference signal generation circuit, 19... Brass processing circuit, 20...
Video tape recorder bZI...playback processing IgIjt
ts, z 2...Digital-analog conversion circuit (D
AC)% 23...Minute m circuit, 211.29...Muting circuit, 30.31...Power amplifier, 23
...Headphone jack% 31...Switch drive circuit, 40...Human DC circuit% 41,42.4F1.5
1... Shift register % 43... And or gate, 44... Recording processing device, 4M"r"Jfja54
．． 51"' Inverter 48... Nando Road, Ja.
...Read-only memory path, ttS...OR circuit%
55...Exclusive-circuit tgIw1.56...Holding circuit, 60.61...Operation amplification l! %62 - Analog switch circuit, 6S... Holding - path. 70, F1. --Differential amplifier, R,, R,1,
R. R eye *R@ @ -+ls l sRl l eRl
'l'''#R1m'''Resistance-DL, DL,
−°°Emission luminescent iodine e, @, c eyes #C3l #C@
@ *C* Hecl & ”・Capacitor, 8・・
・Switch, Trl, Tr,...Transistor. Representative of the originator Patent attorney Fukue Bumon Figure 6 Figure 7

Claims (1)

[Claims] In a digital recording and reproducing apparatus, the apparatus includes a recording system that converts an analog signal into a digital signal and places it on a magnetic tape, and a reproducing system that converts the digital signal reproduced from the magnetic tape into the original analog signal, 1 single signal generating means provided on the input side of the recording system and giving a level substantially equivalent to the maximum level of the output signal output from the reproducing system, and selectively using the reference signal generating means. A digital recording and playback device that allows you to set the optimum recording level for the dubbing tape recorder when dubbing.