JPS5840921A - Flip-flop circuit and frequency dividing circuit - Google Patents

Abstract

PURPOSE:To realize a flip-flop circuit which has a function of an inverter in addition to its normal working, by using a control circuit which always sets a circuit of one side under an open state regardless of an input signal. CONSTITUTION:NAND circuits N1 and N2 which function as the 1st circuit containing the input and output connected in a crossed state to each other have an R-S type flip-flop (FF). NAND circuits N3 and N4 are added to the input of the 1st circuit to form a J-K type FF1. Then the output of a gate circuit G1 is connected to the input of the circuit N2 to form a control circuit 2 which sets the circuit N2 under an open state regardless of the input signal. Thus an overall FF circuit is obtained. This FF circuit functions as a normal J-K type FF when the control signal is 0 and then as a mere inverter when the control signal is 1 respectively. Such FF circuits are combined to easily form a variable frequency dividing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to flip-flop circuits and frequency divider circuits.
The present invention relates to a flop circuit and a frequency divider circuit that can easily form a variable frequency divider circuit.

In recent years, with the increasing integration (IC') of devices such as electronic watches and player motor control, various frequency dividing circuits have been used. Among these, there is a strong desire to realize a variable frequency divider circuit that can easily change the frequency division ratio.

Conventionally, variable frequency divider circuits have configurations such as (1) one that uses a resettable counter, and (2) one that prepares multiple dividers in advance and switches between them, but both require a large number of elements and require an integrated circuit. It has the disadvantage that it is troublesome to convert.

An object of the present invention is to provide a flip-flop circuit (referred to as FF) that can easily constitute a variable frequency divider circuit that eliminates the above-mentioned drawbacks, and a frequency divider circuit using the flip-flop circuit.

The OFF of the present invention is an FF1 formed by including a first circuit and a second circuit in which respective inputs and Tagata are cross-connected.
The circuit C includes a control circuit that always maintains an open circuit regardless of the circuit input signal K of either the first circuit or the second circuit.

The first frequency dividing circuit of the present invention includes a first circuit and a second circuit whose respective inputs and outputs are cross-connected. m (a positive integer of 2 or more) OFF circuits comprising a control circuit that always keeps one of the circuits in an open state regardless of the input signal K, and a holding circuit that always maintains the output of the control circuit in an open state. It includes a cascade connection circuit with n (m(n)) FFs that are equipped with the control circuit or not equipped with the control circuit.

The 20th frequency divider circuit of the present invention includes a first circuit and a second circuit whose respective inputs and outputs are cross-connected. m(2) with an external control input terminal to one circuit
The input of the skeleton control circuit includes a control circuit that turns either one of the Ill circuit and the second circuit in the FF into an open state regardless of the input signal K. n(m
a cascade connection circuit with (n) second type OFFs;
11 O, including a control circuit that is connected to the external control input terminal of each type 1 OFF and always keeps either the first circuit or the second circuit in an open state regardless of the input signal K. It consists of

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the OFF mode of the present invention.

The NAND circuit Nl and NAND circuit N2, which are integrated circuits whose respective inputs and outputs are cross-connected, are R-8.
It is composed of a type FF and has a NAND circuit N3 and NA at its input.
An ND circuit N4 is added to form an FFI at J-,
The first embodiment is OFF because the output of the gate circuit G1 is connected to the input of KN, and a control circuit 2 is formed which keeps N3 open regardless of the input signal K.

Next, the operation of the FF with K is explained.

However, when %QI is given as the control signal N, G
The output of 1 is 111, which is given as NzK. In this case, the form F'FI at J- is -'0' at J- and the output Q,
Q maintains its initial state regardless of the input signal pulse CpK, and when J-total 'O,' is 'l#, Q es ' Q, 'Q is stable at 11#, and at J-11, IK = 10g, Q + '
l, 'Q g+a t Q # stabilizes, J child '11
At 'K' and '1', it operates as a normal J-type FF in which Q and Q are inverted for each input signal pulse.

Next, when %II is given as 1 control signal N, G
The tO output is %O#, which is applied to the input of N2. ζO result NsO output Q is always %II, ie, open circuit, regardless of the input signal pulse CpK. This result N
The output QK of 1 corresponds to CpK, and its inverted pulse is output.

That is, in the FF of this fourth embodiment, the control signal N is %0.
When N is 1, it operates as a normal J-type FF, and when N is 1,
1', k operates as a simple inverter circuit.

It can be seen that when a branching circuit is constructed using the FFs of the third embodiment, it becomes a type of variable frequency dividing circuit that does not divide the frequency.

FIG. 2 is a circuit diagram showing a second embodiment of the OFF mode of the present invention.

This l! The circuit of the example is a KIL (Integrated Injection Logic Int) as shown in Figure 3.
egrat@d Injection: [, ogle
) is formed by a 7tT type FFII and a control circuit 12. This T-type FFII is known from Japanese Patent Application Laid-Open No. 55-78622rI "L Flip-Florap Circuit" by Kent F-Smith.

This TUFF consists of the cross-coupled inputs and outputs of G), G13, and G13 as its control means.
, , ~G17, and further includes a reset input gate G□
It has 8. This T-shaped W11 is cross-coupled gated in response to the input signal pulse TVc.

The control circuit 12 is composed of a gate G1, and one of its two output terminals is a reset gate G1. output terminal and F
The input terminal Km of the F control gate 01m is connected to the input terminal Km, and the other output terminal is connected to the input terminal of the cross gate G1s.

Next, the operation of Jin's second embodiment OFF will be explained.

First, when %0# is given as the control signal N, the two outputs of the gate Gl are both lc%1#, that is, in the open circuit state, so even if this gate G50 is added, T
The operation of the FFII remains unchanged.

Next, when %1j is given as 1 control signal N, the two outputs of gate G19 are both 1/C%OI (nearly shorted to the ground point and in good condition), so 01401m
The output of is always in the %lI state (open circuit state) regardless of the input signal 4#. This result is goo) G14. When Gll simply operates as an inverter, it becomes K, so the output signal of the inverted waveform corresponding to the input signal TK is Ql,
(Sent from h.

That is, in this second embodiment OFF, the control signal K is 10
When it is 1, it operates as a normal T-type FF, and the example is 11#.
When , it operates as a simple inverter circuit.

Similarly to the OFF of the first embodiment described above, the FF of this embodiment of Iris 2 is divided by 2 when N, %oI, N-%II
In this case, K becomes a type of non-dividing variable frequency dividing circuit.

FIG. 4 is a circuit diagram showing a third embodiment of the OFF mode of the present invention. This FF consists of a T-type FF 21 using KI"L and a control circuit 22, as in the second embodiment. The difference from the circuit of the second embodiment is that the FF 21 has a reset circuit. There is no Wt<G)01m) in Fig. 2.Therefore, the gate G2 and gate of the control circuit are those with 3 output terminals, and each Gg)GH*Gg405g
is connected to the input terminal of

The operation of this embodiment OFF is also similar to the FF of the second embodiment described above, when the control signal N is O#, the gate G8.
The output becomes 11# (open circuit state), FF21 operates normally, and the control signal N-% (k is goo when 11)G,
The output of l is %QI, which is the gate oat, Glin (
) i−, so the outputs of these gates are always tlz (open circuit state), and the input signal T is applied to the gates as
r, asvhGxx, and an inverted signal is obtained as output Q.

Therefore, it can be seen that the FF of this third embodiment is also a kind of variable frequency divider circuit that can divide the frequency by 2 and does not divide the frequency by 2.

The OFFK of the present invention has been described above in detail using three embodiments, but it is clear from the previous explanation that these embodiments of the present invention OFF simply add one gate as a control circuit to the normal n. So, change the normal FF to the original FF.
It is possible to switch between operation as an inverter and operation as a mere inverter using a control signal.

That is, the OFF of the present invention has the effect that Fli'' having multifunctional characteristics can be obtained with a simple configuration.

Next, a frequency dividing circuit of the present invention constructed using the above-described FF of the present invention will be explained.

Figure 5 is a circuit diagram showing a first embodiment of the 10 frequency divider circuit of the present invention.

The above-described embodiment of the FFolll of the present invention shown in FIG. In order to keep the input of the control circuit at a low level, the human power terminal k is grounded, and 1 (n = IK) of the shape FF FF1 is connected to the output terminal Q. The circuit of this embodiment is constructed by sequentially connecting the input terminals Cp to form a cascade circuit.

Next, the operation of the circuit of this embodiment will be explained.

First, it is assumed that the terminals of all J are maintained at the %II level and a reset signal R is applied so that they are reset at the trailing edge of the input signal pulse.

In this state, when %QI is first given as the 5 control signal N, the output of the control circuit is 11# (open circuit state) as described above, and since the control terminal N of KFF is grounded, Since the output of the control circuit is also 11' (open circuit state), FFI-FF4 operates normally as a J- type FF. Therefore, the input signal pulse/amount is each *<F'
As a result of frequency division by 2, the output signal pulse 0 becomes the input signal pulse ei divided by y16.

Next, when 111 is given as the control signal N, the output of the control circuit of KFF and ~FF4 is %oI as described above.
Since one of the FF cross circuits is opened, FF'2 to FF
4 does not operate as a mere inverter circuit, while F
Since F1 is always in the state of Nm%01, it operates normally as a type FF regardless of the control signal k.

Therefore, in this case, the output signal pulse 0 is the input signal pulse 1 divided by V2.

That is, the frequency dividing circuit of the first embodiment is a variable frequency dividing circuit that divides the frequency by I/la for the control signal N101, and divides the frequency by W for the control signal N101.

As described above, by using the FF of the present invention, a variable frequency dividing circuit can be obtained very easily.

FIG. 6 shows a second embodiment of the first frequency dividing circuit of the present invention.

The difference from the circuit of the first embodiment shown in FIG.
Instead of the FFI shown in the figure, an ordinary J-type FF OFF'1, which does not have the control circuit 2 of the FF of the present invention shown in FIG. 1, is used. In this way, FF'1 is not related to the control signal at all, so like the circuit of the 4-channel embodiment of this embodiment, the frequency is divided by I/2/17
This becomes a variable frequency divider circuit that divides the frequency by 16. Compared to the first embodiment, even if a normal J-type FF is used as the FF'1, it has a negative effect.

FIG. 7 is a circuit diagram showing a third embodiment of the first frequency dividing circuit of the present invention.

The circuit of this embodiment uses the FF11.Ii-TE12 which is the OFF mode of the present invention using the I''L inverter shown in FIG.

However, the T input gate G27 in FIG. 4 is combined into a single input gate G31. Gate G8. ~G34 is the reset control circuit of the circuit,
The FF11 and FFI form a known p frequency divider circuit. The FF110 control circuit terminals are grounded to maintain the input of the control circuit at a low level. The circuit of this embodiment is constructed such that a control signal N is directly applied to the control circuit terminal N of the circuit.

Next, we will explain the operation of this circuit.10 First, when the 1 control circuit signal N is 101, the outputs of both the control circuits, KFFII and FFI, are in an open state, as is clear from the explanation in the video. Since it operates as a normal T-type FF and the output of the gate G84 is 11' (open circuit state) K, the angularly divided wave of the input signal pulse 1 is output as the output signal pulse 0.

Next, when the % control circuit signal N is 111, FFI.

operates as a simple inverter circuit, and the gate G1
The output of FF11.4 is 10I. Regardless of the output of FF12, the output of gate G33 is 11', so gate Ga
The output of No. 11 becomes %QI, and FPII and Fxs are no longer reset. (The circuit configuration is such that it is reset when the Q outputs of FFII and Flll are both 111.) Therefore, FFII operates as a normal divide-by-2 circuit, and FF1. Since it operates as a non-frequency dividing circuit, the frequency divided wave of the input signal pulse @1 is output from the output of this circuit as the output signal pulse SO.

In other words, the circuit of this third embodiment also has a very simple configuration, and a variable frequency dividing circuit with frequency division by 112 and frequency division by 43 can be obtained.

FIG. 8 is a circuit diagram showing an embodiment of the second frequency dividing circuit of the present invention.

The difference from the circuit of the first embodiment of the 10th frequency divider circuit shown in FIG. 5 is that the gates forming the control circuits included in FF1 to FF4 in FIG. Goo)G
40, and FF', ~F〆4 is provided with an external control input terminal Nl to either the first circuit or the second circuit forming the FF cross circuit, and a gate circuit G4 is connected thereto.
0, the control signal N can be applied via 0. Therefore, like the circuit of the first embodiment described above, this circuit also divides the frequency by 1μ6 using the control signal N −% Q #, and divides the frequency by l(,,
, % l # stops the variable frequency divider circuit of Ge2 frequency division.

In the circuit of this embodiment, the gates of the control circuit are not provided in each FF but are provided in one gate, so the fan-out number is limited to the number of gates 04G, but if the number of stages is small, the overall element This has the effect of making IC implementation easier in terms of reducing the number of devices.

The frequency divider circuit of the present invention has been described in detail using four embodiments, but in all cases, the use of the OFF function of the present invention has the effect that the circuit can be configured very easily. .

In the explanation so far, the FF has been used as an example of a J-type FF using a NAND circuit, or an IILT-type FFt, but the gist of the present invention is not limited to this. For example, a J-type FF using a NOR circuit It is also applicable to other types of OFF such as type FF and D type FF, and although a gate circuit is used as the simplest example of the control circuit, it is also applicable to other circuits with the same function. Needless to say.

Furthermore, it is of course possible to simply use a grounding circuit as a holding circuit for holding the output of the control circuit in an open state, and use other circuits having the same effect. It should be noted that the number of FFs used in the frequency dividing circuit is not limited to that of the embodiment, and it goes without saying that the number of FFs used in the frequency dividing circuit may be changed depending on the frequency dividing ratio.

As described above in detail, the nine ways of OFF of the present invention are extremely simple control circuits that open either one of the cross-connected first circuit and second circuit forming the FF regardless of the input signal. (in principle, one gate), it has the advantage of providing a multifunctional FF that performs normal FF operation and operation as a mere inverter.

Furthermore, the frequency divider circuit using the FP of the present invention can easily configure a variable frequency divider circuit due to the multifunctionality of the FF. There is no need to prepare a frequency dividing circuit and a switching circuit, which was difficult in the past.
It has the effect that C conversion can be easily performed.

[Brief explanation of drawings]

1, 2, and 4 respectively show the first flip-flop circuit of the present invention. Circuit diagrams showing the second and third embodiments, Figure 3 is an explanatory diagram of the I'L gate, Figure 5, Figure 6
7 and 7 respectively show the first frequency dividing circuit of the first embodiment of the present invention. FIG. 8 is a circuit diagram showing an embodiment of the second branch circuit of the present invention. In the figure, 1...J- is a type FF%1222...control circuit, 11.21...T-type FF, Nl-
N4...NAND circuit-Gl, Gll ~G
191 G21~02a #G31~G34...
・・Gate, FF1~FF4 v FF'I F'2
~F-...Flip-flop circuit (FF), N
・Old...Control signal (control signal terminal) % Nl...
...External control input terminal, 61...Input signal pulse, 6o Old...Output signal pulse. A picture of the opening eA' of the box

Claims (1)

[Claims] +1) A first device whose respective inputs and outputs are cross-connected.
In a flip-flop circuit formed including a circuit of $1E1 and a second circuit, control to always keep either one of the circuit of $1E1 and the second circuit in an open state 11 regardless of an input signal. A flip-flop circuit is characterized by a circuit. (2) In a flip-flop circuit formed by including a first circuit and a second circuit whose respective inputs and outputs are cross-connected, either one of the tenth circuit and the 111120 circuit is connected regardless of the input signal. m (a positive integer of 2 or more) flip-flop circuits each having a control circuit that always keeps the circuit open; and the control circuit having a holding circuit that always keeps the output of the control circuit open. A frequency divider circuit characterized in that it includes a four-way circuit with n (m(n)) flip-flop circuits that are not equipped with the control circuit. (3) A first circuit whose inputs and outputs are cross-connected. m (a positive integer of 2 or more) having an external control input terminal to either one of the first circuit and the second circuit ) of the first type of flip-flop circuit and a control circuit that opens either the first circuit or the second circuit in the flip-flop circuit regardless of an input signal. A cascade connection circuit with n (m<n) second type flip-flop circuits having a holding circuit that always keeps the output open or not having the control circuit, and each of the m flip-flop circuits. and a control circuit connected to the external control input terminal of the first type flip-flop circuit to always keep one of the first circuit and the second circuit in an open state regardless of the input signal. A frequency divider circuit featuring: