JPH026682Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a pulse selection circuit.

A conventional pulse selection circuit has a configuration that requires a pulse selection signal to selectively output a first pulse input signal and a second pulse input signal.

A conventional example will be explained below with reference to the drawings.

FIG. 1 shows the configuration of a conventional pulse selection circuit, in which 1 is a first pulse signal input terminal, 2 is a second pulse signal input terminal, 3 is a pulse selection signal input terminal,
4 is an inverter, 5 is the first AND gate, and 6 is the first
2 is an AND gate, 7 is an OR gate, and 8 is a pulse signal input terminal. In the figure, the first pulse signal input terminal 1 is connected to one input terminal of the first AND gate 5, and the second pulse input terminal 2 is connected to the second AND gate 6.
are connected to one input terminal of each. Further, the pulse selection signal input terminal 3 is connected to the other input terminal of the inverter 4 and the first AND gate 5, and the output terminal of the inverter 4 is connected to the second AND gate 6.
are respectively connected to the other input terminal of the . Each output terminal of the first AND gate 5 and the second AND gate 6 is connected to an input terminal of the OR gate 7, and an output terminal of the OR gate 7 is connected to a pulse signal output terminal 8.

Based on the above configuration, the operation of the conventional pulse selection circuit will be explained with reference to FIGS. 1 and 2.

Note that FIG. 2 shows operating waveforms of each part in FIG. 1.

If the pulse selection signal input terminal 3 is initially at "H" level as shown in FIG. gate 6
The output signal also becomes "L" level. On the other hand, the
The output signal of the 1AND gate 5 becomes equal to the signal waveform inputted from the first pulse signal input terminal 1 as shown in FIG. 2b. As a result, the output signal of the OR gate 7, that is, the output signal of the pulse signal output terminal 8 becomes equal to the input signal of the first pulse signal input terminal 1.

Next, when the pulse selection signal input terminal 8 changes to the "L" level as shown in FIG.
Since the output signal of the 1AND gate 5 becomes "L" level and the output signal of the inverter 4 becomes "H" level, the output signal of the second AND gate 6 becomes the second pulse signal input from the second pulse signal input terminal 1. It becomes equal to the signal waveform in Figure c.

Therefore, when the pulse selection signal input terminal 3 is at the "H" level, the input signal of the first pulse signal input terminal 1 is output from the pulse signal output terminal 8, and the pulse selection signal input terminal 3 is at the "L" level. ” level, the input signal of the second pulse signal input terminal 2 is output from the pulse signal output terminal 8.

As mentioned above, the conventional pulse selection circuit
In addition to the pulse signal input terminal 1 and the second pulse signal input terminal 2, a third pulse selection signal input terminal 3 is required independently, and therefore, due to the circuit configuration, a circuit for sending out the third signal is additionally required. Therefore, this has become a bottleneck in improving the performance and downsizing of the pulse selection circuit.

This idea was created by focusing on the points mentioned above.
It is an object of the present invention to provide a pulse selection circuit which eliminates a circuit for generating a pulse selection signal and an input terminal for this pulse selection signal, and which is configured to obtain the same function.

Two embodiments of the present invention will be described below with reference to the drawings.

Note that the same configurations as those of the above-described conventional example shown in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

FIG. 3 shows a first embodiment of the present invention, in which 9 is a binary up counter with count output terminals 9C,
It has a clock pulse signal input terminal 9I and a reset signal input terminal 9R. In the figure, the first pulse signal input terminal 1 is connected to the first AND gate 5.
The second pulse signal input terminal 2 is connected to the input terminal of the OR gate 7 and the reset signal input terminal 9R of the binary up counter 9. Next, the count output terminal 9C of the binary up counter 9 is connected to the input terminal of the inverter 4 and the input terminal of the second AND gate 6, and the output terminal of the inverter 5 is connected to the input terminal of the first AND gate 5. There is. Further, the output terminal of the first AND gate 5 is connected to the clock pulse signal input terminal 9I of the binary up counter 9, and the output terminal of the second AND gate 6 is connected to the input terminal of the OR gate 7.
Further, the output terminal of the OR gate 7 is connected to a pulse signal output terminal 8.

Based on the above configuration, the operation of an embodiment of the present invention will be described below with reference to the drawings.

Incidentally, FIG. 4 shows operating waveforms of each part in FIG. 3.

First, the operation of the binary up counter 9 will be explained. In the reset operation of the binary up counter 9, when the reset signal input terminal 9R is at the "H" level, the count output terminal 9C is asynchronously changed to the "L" level. Furthermore, the counting operation of the binary up counter 9 is performed using the clock pulse signal input terminal 9I.
When the clock pulse signal input terminal 9I changes from the "H" level to the "L" level twice,
The count output terminal 9C is changed to "H" level.

Now, as shown in Figure 4b, the second pulse signal input terminal 2 is held at the "L" level for more than two cycles of the pulse signal as shown in Figure 4a, which is input from the first pulse signal input terminal 1. Then, the count output terminal 9C of the binary up counter 9 becomes "H" level. Therefore, the inverted output of the inverter 4 becomes "L" level, and the output of the first AND gate 5 also becomes "L" level as shown in FIG. 4c. As a result, the binary up counter 9 does not perform a counting operation, so that the count output of the binary up counter maintains the "H" level. On the other hand, the output signal of the second AND gate 6 is
The output of the second AND gate 6 is given as the logical product of the input signal of the pulse signal input terminal 1 and the output of the count output terminal 9C of the binary up counter 9, and the output of the second AND gate 6 is given as the logical product of the input signal of the pulse signal input terminal 1 and the output of the count output terminal 9C of the binary up counter 9. Equal to the input signal. Therefore, the output signal of the pulse signal output terminal 8 is also equal to the input signal of the first pulse signal input terminal 1.

Next, when a pulse signal is inputted from the second pulse signal input terminal 2, the frequency and the "H" level time in one cycle are almost equal to the input signal of the first pulse signal input terminal 1, the second pulse signal If input terminal 2 is “H level”, binary up counter 9
The reset signal input terminal 9R of the inverter 4 becomes "H" level, the count output terminal 9C becomes "L" level, and therefore the output signal of the inverter 4 is inverted and becomes "H level". As a result, the counting operation is performed by the pulse signal input from the first pulse signal input terminal 1 via the first AND gate 5, and then the second pulse signal input terminal 2 goes to "L".
Even if the level is high, the second pulse signal input terminal 2 will be at the "H" level before the first pulse signal input terminal 1 changes from the "H" level to the "L" level twice, so the binary up counter 9 The count output terminal 9C of the
The “L” level output of 2AND gate 6 remains unchanged.
The output signal of the pulse signal output terminal 8 becomes equal to the input signal of the second pulse signal input terminal 2.

The signal shown in FIG. 4e is the output of the OR gate 7, that is, the signal appearing at the pulse signal output terminal 8.

As described above, one embodiment of this invention simplifies the circuit configuration of the conventional example described above by omitting the pulse selection signal, but its pulse selection output is basically the same as that of the conventional example. can be obtained. That is, when inputting a pulse signal from the first pulse signal input terminal 1, if the second pulse signal input terminal 2 is at "L" level, the pulse input signal from the first pulse signal input terminal 1 is input to the pulse signal output terminal. When a pulse signal is input from the second pulse signal input terminal 2, the second pulse input signal is output from the pulse signal output terminal 8.

Next, embodiments of the present invention will be described with reference to FIGS. 3 and 5.

The second embodiment of this invention has the same circuit configuration as the first embodiment described above, and if a pulse signal as shown in FIG. 5 is input to this circuit configuration,
This is an example in which the pulse output of this pulse signal can be stopped. In FIG. 5, a indicates a pulse signal input from the first pulse signal input terminal 1, b indicates a signal input from the second pulse signal input terminal 2, and c indicates a signal output from the pulse signal output terminal 8. There is. That is, if the second pulse signal input terminal 2 is at the "L" level, the pulse signal input from the first pulse signal input terminal 1 is output from the pulse signal output terminal 8, as in the first embodiment described above. Ru. Next, the second pulse signal input terminal 2 becomes “H”
When the level is reached, the reset signal input terminal 9R of the binary up counter 9 becomes "H" level, and
The counter output terminal 9C becomes "L" level. As a result, the output of the second AND gate 6 also becomes "L" level, the pulse signal output terminal 8 becomes "H" level like the second pulse signal input terminal 2, and the pulse signal of the first pulse signal input terminal 1 is output. stop. Therefore, in the second embodiment of this invention, the output of the pulse signal from the first pulse signal input terminal 1 and the output from the pulse signal output terminal 8 can be ON-OFF controlled by the input signal from the second pulse signal input terminal 2. can.

As explained above, the present invention can reduce the number of input terminals compared to conventional pulse selection circuits by omitting the pulse selection input terminal 3 from the circuit configuration. Because it can save money, it has the advantage of making the IC package smaller and simplifying the peripheral circuitry, and it also allows for new applications of the circuit, such as 2
This is highly effective in applications such as input circuits for single pulse signals.

In addition, the present invention has a wide range of applicability and is highly versatile, since there is no restriction on the oscillation circuit that generates the first pulse input signal, and any signal that changes as required can be used as the second pulse input signal. It will be excellent. Moreover, since it is composed of logic elements and counters, it is easy to integrate it into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional pulse signal selection circuit, FIG. 2 is a waveform diagram showing operating waveforms of each part in FIG. 1, and FIG. 3 is a circuit diagram showing a first embodiment of the present invention. Figure 4 is a waveform diagram showing the operation of each part in Figure 3, and Figure 5 is a second embodiment of the present invention, in which operation waveforms different from those in Figure 4 of the first embodiment are obtained for each part in Figure 3. FIG. 1...First pulse signal input terminal, 2...Second pulse signal input terminal, 3...Pulse selection signal input terminal, 4...Inverter, 5...First AND gate,
6...2nd AND gate, 7...OR gate, 8...
...Pulse signal output terminal, 9...Binary up counter, 9C...Binary up counter 9
9I: the clock pulse signal input terminal of the counter 9, 9R: the reset signal input terminal of the counter 9.

Claims (1)

[Claims for Utility Model Registration] A first pulse signal input terminal to which a first pulse signal is input, a second pulse signal input terminal to which a second pulse signal is input, and the first pulse signal input terminal is a first AND gate connected to the first input terminal; and a binary amplifier, the output terminal of the first AND gate being connected to the clock input terminal, and the second pulse signal input terminal being connected to the reset input terminal. a counter; an inverter having an input terminal connected to a counter output terminal of the binary up counter and an output terminal connected to a second input terminal of the first AND gate; a second AND gate with the counter output terminal of the binary up counter connected to the second input terminal; an OR that connects a signal input terminal to a second input terminal and outputs one of the first pulse signal or the second pulse signal;
A pulse selection circuit with a gate.