JPS5846779A - Mask pulse generating circuit - Google Patents

Abstract

PURPOSE:To simplify the adjustment of a mask pulse generation position and to output data accurately, by generating a pulse, which masks the clock line signal and the framing code in a character broadcasting packet, in accordance with the superposing position of the character broadcasting packet. CONSTITUTION:A sampling pulse corresponding to the position where a character broadcasting packet is superposed is generated in a vertical position counter 22 in accordance with the composite video signal from a video detecting circuit 12, and the character broadcasting packet is sampled in a waveform shaping circuit 13 and is inputted to a sampling circuit 14. A clock line signal is extracted in a clock line signal detecting circuit 16, and continuous clocks are generated from a clock pulse generating circuit 17 synchronously with this signal. Various data are outputted from the circuit 14 by the output of this circuit 17 and are inputted to a framing code detecting circuit 18, and the start part of a buffer memory 15 is set by the output of the circuit 18. Thus, the adjustment of the mask pulse generation position is simplified to output data accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask pulse generation circuit that is effective for use in systems that receive and reproduce television signals containing text information and the like.

In a teletext broadcasting receiver, image information such as a single character figure is transmitted by a digital signal, which is sampled using a data sampling pulse, and the data necessary for display is stored in a turn memory and assembled. The contents of this turn memory are read out in accordance with the synchronization signal of the display device. In teletext broadcasting using television signals, the main character of the teletext broadcast during the vertical retrace period,
is inserted and transmitted. In the teletext mother packet,
As will be explained in detail later, on the receiving side, which includes a clock run-in signal, a framing code, etc., and a dezotal signal to be transmitted, the data sampling signal is first synchronized with the clock run-in signal. The data following the clock run-in signal is sampled and
Temporarily stored in the file circuit. The sampled r-event also contains a claiming code, and this framing code is used as an indicator to indicate the beginning of data. When this framing code is detected, subsequent data is stored in the 74177 circuit. will be started.

As mentioned above, the black and crank-in signals and the data sampling pulses are processed in the sampling pulse generation circuit so as to be synchronized with each other, but before that, the black and clan-in signals are processed accurately in the teletext signal. , it is important to mask and extract it from the front. Further, the framing code is a predetermined code, and its position is detected by a framing code detection circuit. Therefore, when extracting the 7-raming code from a teletext/monograph, a mask pulse is generated that covers approximately the position of the 7-raming code at the timing when the 7-raming code is expected to exist, and the 7-raming code is extracted. Introduced into the matching code detection circuit ◎As mentioned above, when receiving teletext broadcasting.

It is necessary to generate multiple mask pulses in order to extract the clock run-in signal or framing code. Conventionally, this type of mask pulse is based on the horizontal synchronization signal. For example, when the horizontal synchronization signal is Monostable multi-double! In addition to the circuit, create a nonalus of a certain width and use this as the reset signal for Kakunta. The kakunta counts the black and red signals, and when the count value reaches a certain value, it is detected by a logic circuit, and the mask is output from the logic circuit. According to this method, when adjusting the timing of occurrence of the mask tsutsurus, the monostable multi-pibre! It is necessary to adjust the time constant of the circuit and shift the reset timing of Kakunta. However, the insertion position of teletext, yak, and t with respect to the horizontal synchronization signal is not necessarily a fixed position, and may fluctuate depending on various factors such as circuit conditions. For this reason, when mask pulses are generated by the above-mentioned means, there are disadvantages in that data cannot be obtained accurately and the mask pulse generation position must be adjusted frequently. This was done in order to deal with the situation in which the superimposition position of teletext packets fluctuated within the horizontal scanning period. It is an object of the present invention to provide a mask pulse generating circuit that generates a mask pulse by following the superimposed position of a broadcast/false.

Embodiments of the present invention will be described below with reference to the drawings.

First, the format of the television signal used in teletext broadcasting will be explained.

The TV signal used in teletext broadcasting is set as shown in Figure 1.
-), Cb> indicates the vertical blanking period portion of the first field and the next field of the composite video signal, ■ is the vertical synchronization signal ◎The rear part of this vertical blanking period portion, for example, the previous field 20th H after the end (H; 1
(horizontal period), there are 4 teletext broadcasts) 1 * :l
is set. The format of this teletext packet,
H is a horizontal synchronizing signal, 5 is a color burst, 0 is a teletext signal, and 2 is formed by the header part C1 information part 1. . Further details of this teletext 4-ket 2 are shown in Figure 1 (d).

Part 6 is the clock run-in (cloc
kru+1in) signal CRI, plating code FC, identification code IDC, etc.

The types of teletext packets 2 include control packets, packets, color code packets, and pattern packets. The information section of the control program contains data indicating what kind of content is sent from the control program.For example, as shown in Figure 1(d), the program code (program number ) PCI, PO2, easy number PAI.

In addition, the information section of the color code packet, which includes PA2, etc., includes color code packets, /4 turn data, etc., as shown in Figure 1).
D-D) etc. are included.

In the header part 6, the clock run-in signal CRI is a signal for adjusting the phase of the pulses necessary for sampling the data in this teletext/backket. The framing code FC is a code that indicates the beginning of data. The identification code IDC indicates the display format or transmission signal format.

If a mixture of programs in various display modes is being transmitted,
This is a code to identify this.

The teletext/foot as described above is processed by a system as shown in FIG. 2, for example.

Reference numeral 11 denotes an input terminal to which the intermediate frequency of a television signal from teletext broadcasting is input. The signal applied to this input terminal is subjected to image detection by an image detection circuit 12. The video-detected composite video signal is sent to a waveform shaping circuit 1 that extracts text broadcasting/transformation and also performs waveform shaping.
3 is input. Further, the composite video signal is input to a synchronization separation circuit 211C that separates a vertical synchronization signal V and a horizontal synchronization signal H.

a vertical synchronization signal V separated from the synchronization separation circuit 21;
Horizontal synchronization signal BFi, correct image position! 22 ◎This vertical position kakun 122 is reset by the vertical synchronization signal V and counts the horizontal synchronization signal H, and outputs a sampling pulse corresponding to the position where the teletext/cut is superimposed. Obtainable.

The sampling signal obtained by the vertical counter 22 is input to the waveform shaping circuit 13. As a result, the waveform shaping circuit 13 extracts the teletext packet described in FIG. 1 and shapes its waveform. The output obtained from this waveform shaping circuit fJ is input to the sampling circuit 14, and the black and crank-in signal detection circuit 1
6 is input.

The black and crank-in signal detection circuit 16 is shown in FIG. 1(d).
It showed. It extracts the clock run-in signal CRI, and the extracted clock run-in signal is the clock aJ? The signal is input to the pulse generation circuit 17. This clock pulse generation circuit 17 has a function of generating continuous clock pulses synchronized with the clock and crank-in signals.

The signal/example is input to the sampling circuit 14,
Used as a demosampling nostril.

In the sampling circuit 14, various types of data as shown in FIG. Stored of
However, the output of the sampling circuit 14 is also input to the framing code detection circuit 18. The framing code detection circuit 18 performs detection by comparing a predetermined framing code with the input code, detects a point where the codes completely match, and then detects the starting point of the data that is stored in the frame memory. This is to set. 7. The ramming code detection circuit 18 is driven by a clock pulse from the horizontal position counter 23, for example.
The horizontal position counter 23 is reset by the horizontal synchronization signal HK from the synchronization separation circuit 21, and counts the clock signal from the clock signal generation circuit 17. The count information of the horizontal position counter 23 is stored in the address circuit. 24 has also been added. The address circuit 24 also receives the previous vertical synchronization signal.

This address circuit 24 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal.

As described above, the contents of the teletext message are stored in the buffer memo IJf5 when the message is received. The data stored in this buffer memory 15 is stored in the microcombi, -! The central processing unit (hereinafter referred to as CPU) SO decodes the data contents of the buffer memory 15. For example, what is the data format and what is the program? By operating the card 40, a command signal for processing weather forecast data can be input. The weather forecast program is specified by the program code shown in FIG.゛For example, if the data of the program code PCI is sending a weather forecast, this program code PCI
I is processed by CPU JO. As a result, the data of this program code PCI is
/4 if it matches the data specified from
y 77 Memo IJ It turns out that data 15 is data for weather forecasting. A command signal for not playing the weather forecast specified by the key 35 is stored in a random access memory (hereinafter referred to as RAM).

The weather forecast pattern data read from the buffer memory 15 is finally stored in the parable turn memory 5xKL as character f-1 symbol data. The color data is stored in color memory 34.

The data read from the notebook memory 15 is stored in the mother turn memory 33 as character data or symbol data, but if the transmission method is a code transmission method, the data read out from the rough memory 15 is stored as character data or symbol data. Decipher the data and extract predetermined character data from read-only memory (hereinafter referred to as ROM), that is,
Furthermore, since it is possible to read out characters, symbols, and graphic data and store them in the turn memory 33, etc.,
A character ROM 39 is prepared.◎ As mentioned above, character and symbol 8 graphic data are stored in the pattern memory 33 based on the data derived from the buffer memory 15. Extracting the mother card only once is enough for character display! .

cannot be obtained. Therefore, every time there is a vertical synchronization period,
And every time a desired program is detected, the above No. 4/-
The mother turn memory 33 is sequentially stored in the turn memory 33.
．． When storing r-y in the color memory 34, the data may be stored at the next address, for example, by inputting address designation data specifying the storage address together with data l.

Said/mother turn memory 33. When data stored in the color memory 34 is read out and displayed, the data in the no-turn memory 33 is converted to DC via the pattern decoder 36, and the data in the color memory 34 is converted to DC via the color decoder 36. and is synthesized at the output interface 31.

Then, it is combined with the composite video signal in a combining circuit 38.

Pattern memory 33. The timing for reading data from the color memory 34 is based on a command signal from the CPU 30.

The CPU 110 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 24. This address data is RAM j
If they match the desired display designation data set in the address data, the read signals corresponding to these address data are sent to the node memory 33. It is added to color memory 34.

The display data is included in the GLODRAM stored in RAM J 2, and the display format can be set in various ways according to changes in this display specification data and switching of the GLODRAM. Teletext broadcasting as described above The signal is processed, but in this device, the signal is processed in black.

The mask pulse generation means for accurately extracting and processing a clan-in signal or a 7raming code is equipped with a percentage feature, and its characteristic components will be explained below.

For the sake of simplicity, the i/4 pulse generation section for the clock run-in signal will now be described with reference to FIG. @ In Figure 3, 41 indicates that the horizontal synchronization signal H separated by the previous synchronization separation circuit 21 is reset.

This counter 41, which is added as a counter signal, is reset by the horizontal synchronizing signal H and calculates the data sampling pulse of the DSP. The data sampling pulse DSP is generated by the above-mentioned black/arm pulse generation circuit 17.
Added from. The count output of counter 41 is input to logic array 42 . This logic array 42 is
It is set so that an output pulse is generated when the count value of the counter 41 reaches a specific value. An output having a pulse width that covers the clock run-in signal is obtained from the first output terminal 42 of the logic array 42, and its generation position (maming) is predicted to be during the clock run-in signal period. It is set in such a position that it

(Hereinafter, the pulse generated at the output terminal 42a will be referred to as the original clock run-in signal mask pulse RCRI.) Furthermore, from the 12 output terminals 42b of the logic array 4j, signals are generated corresponding to the positions of the 7 framing codes. This output terminal 42b outputs a mask pulse whose pulse width is set to sufficiently widen the movement range of the 7 framing codes that are useful for moving the superimposed position of 4 teletext broadcasts. The resulting four pulses are referred to as reference mask pulses RFC. ) The generation positions of the original clock run-in signal mask pulse and the reference mask pulse can be freely changed by changing the logic configuration of the logic array 42. On the other hand, the input terminal 43 has A serial character multiplex signal whose waveform has been adjusted is input. This character multiplex signal is 1. 0 is input to the sampling circuit 14 which can be configured with a shift register and converted from serial to parallel. In this sampling circuit 14, 5. The aforementioned data sampling pulse is used as the clock. The output of this sampling circuit 14 is input to a 7 ramming code detection circuit 18. This framing code detection circuit 18 obtains a 7 framing code detection pulse FDP when the data output from the sampling circuit 14 becomes a 7 framing code (for example, tfllloolol), and a code for data comparison is written in advance. 44 is an AND circuit which inputs the above-mentioned reference mask pulse RFC data sand ring pulse, performs the logical product, and outputs the output pulse from the shift register 4.
6 clock input terminal. This shift register 4
5 is an output pulse Pal of the AND circuit 44 using the framing code detection pulse FDP as a gator input.
The transfer output of this shift register 45, which is used as a clock input, is input to an output conversion circuit 46. This output conversion circuit 46 uses a ROM, and the shift register 14
A conversion code is written in advance so as to generate an output corresponding to the output of No. 6.

The converted output of the output conversion circuit 46 is input to the latch circuit 41. This latch circuit 47 converts the converted output of the output conversion circuit 46 by the output of an AND circuit 48 which takes the logical product of the output from the input terminal 49 and one output of the output conversion circuit 46. do. In this way, each □ pit output inputted to the child circuit 41 is outputted as D! It is applied to one input terminal of each AND circuit 51a to 5ill constituting the selector 50. These AND circuits 51a to 61
Each pit output of the shift register 53 is applied to each other terminal of the shift register 53.

This shift register 53 is the original clock mentioned above.

Clan-in signal mask/Gurus RCRI 1 day! The input is the data sampling curve DIP rough lock. The outputs of each AND circuit 51h to 5Zf are applied to an OR circuit 52, and the output of the AND circuit 52 is used as a normal clock run-in signal mask I4 pulse.

Next, an example of operation will be described using timing charts shown in FIGS. 4, 5, and 6. Now, for simplicity, the reference mask pulse R
Assuming that the pulse width of the FC is equal to the width of 8 cycles of the data sampling pulse DSP, 8 pulses will be output from the AND circuit 44. First, let us explain the signals in each figure. Each figure (a) shows the data 1 sampling source DSP, and each figure (c) shows the female hand multiplexed signal, the clock 2 input signal CRI and the 7 timing code FC part. (d)
are the Hari-Rodz run-in signal mask/Yars RCRI and the reference mask pulse RFC, which are obtained from the logic array 42 ・Each figure (@) ~ (1) Fi, each bit of the shift register 53 Next, each figure (c) shows the frame code detection/parallel.

Furthermore, each of the figures (n) to (u) is the output of each bit Q, to Q1 of the shift register 145. 'And in each figure ←) is the output of the AND circuit 44. Figure 4 is an example in which the clock run-in signal CRI has a significant phase lag than the position of the original clock and crank-in signal mask pulse RCRI, and also compared to the example in Figure @5 #i @4. An example in which the phase of the clock run-in signal CRI is advanced, and furthermore, FIG.
This is an example in which the phase of FDP C, output pulse P of AND circuit 44
Shift black al.

By operating in this manner, the output of the shift register 45 becomes the reference mask pulse RFC,
The mutual phase relationship with the Freight ring code FC at the time of lj will be expressed.

On the other hand, the original clock run-in signal RCRI d, shift)
Since it is input to the register 58 and transferred by the data 1 sampling pulse DIP, each bit of the shift register 51 (Qe''=Qy) is outputted from N pieces (in the illustrated example) at different positions for each cycle of the data 1 sampling pulse. F1a) mask/medium pass cases will occur.

Therefore, the pressure of the shift register 45 indicates the positional relationship between the reference mask pulse RFC and the training code FC, and the reference mask pulse RFC and the original black and crank-in signal mask/4 pulse RCRI are always in a constant relationship. From the output of the shift register In the example, the output Q! is shown in (1) of the same figure. is derived from the AND circuit 61h, 10ville
') The input signal CRI can be effectively masked. In addition, in an example of FIG. 5, the output Q4 shown in the figure (0)
is derived from the AND circuit 51@, and in the case of the example shown in FIG. Using the black and crank-in signal mask pulses, a mask af signal with a different phase is generated by the shift register 53'' near the position of the black and clan-in signals, and the /4 pulse is most suitable for masking the black and clan-in signals. The pulse can be taken out by opening any one of the AND circuits 51a to 61. For this purpose, while creating a reference mask pulse, the reference mask pulse and the data sampling pulse can be used to create a , the 7-ray imaging code from the 7-ray framing code detection circuit is transferred to the shift register 45, and the output state of the shift register 45 is used to determine the phase positional relationship between the framing code and the reference mask pulse. Based on this, one of the AND circuits 5'la to 51h is
We are creating a signal to select one. Here, the transmitted clock run-in signal and framing code are always in a fixed relationship, and the original clock run-in signal mask pulse output from the logic array 42 and the reference mask/4 pulse are This is a fairly constant relationship. In order to obtain the above-mentioned operation, a conversion table as shown in Table 1 below is stored in the output conversion circuit 46.

Note that the latch/4 pulse applied to the input gate 49 of the AND circuit 48 is derived from the following circuit at the following timing.As mentioned above, according to this device, the teletext IJi,
Even if the superimposition position of the clock signal fluctuates with respect to the horizontal synchronizing signal, the mask pulse for extracting the clock run-in signal within the packet moves to follow, and an accurate lock run-in signal can always be obtained. The above explanation is based on the circuit for creating the mask path of the Kuro-Kranin No. 4M, but if other types of masks/4 paths are needed, the circuit shown in Figure 3 may be used as a representative circuit. data selector,
This is made possible by providing delay shift registers, delay registers, and quarays in order to generate the original pulse of each mask pulse.

Table 1 A@jJAIA4A4A5A4A7 D6DID1DI
D4DIDaD7D@100000000000000
10 00000001 ooooooooo for other addresses.

As mentioned above, this invention is telecasting)
Even if the superimposition position of the 4 bits fluctuates within the horizontal scanning period, the t4 pulse for masking the clock run-in signal or framing code in the teletext background (-) is generated by following the target signal position. It is possible to provide a mask pulse generation circuit that can perform the mask pulse generation circuit.

[Brief explanation of the drawing]

Figures 1 (-) to (•) are explanatory diagrams showing examples of formats of television signals handled in teletext broadcasting, Figure 2 is a configuration explanatory diagram showing one embodiment of the present invention, and Figure 3 1 is a circuit diagram showing a main part of the present invention, and FIGS. 4, 5, and 6 are signal waveform diagrams of various parts shown to explain an example of the operation of the circuit shown in FIG. 3, respectively. 14... Sampling circuit, 16... Clock 2-in signal detection circuit, 17... Clock i4 pulse generation circuit, 18... Framing code detection circuit, 21...
・Synchronization separation circuit, 41...Kakunta, 42...Knock array, 44...AND times, abbreviation, 45.53...
・Shift register, 46... Output conversion circuit, 41...
・Latch circuit, 50...Data select! ! . 8εbiS wealth; 39 −− ν police −ψ −−

Claims (1)

[Claims] In a system where packets composed of digital signals are sent superimposed between intermittent signals such as horizontal synchronization signals, the intermittent signals are used as reset/# pulses, data sampling pulses are counted, and the counted value is a reference mask pulse having a degree corresponding to the position of a framing code that marks the start of data in the node correspondingly, and a constant relationship with this reference mask pulse,
means for generating an original mask/parallel whose width corresponds to the serial length of the code to be masked in the packet at a predicted position of the code; The output of the sampling circuit that samples the original mask/4 pulses is added to the 7 framing code detection circuit which detects the 7 framing codes and outputs a framing code detection signal, and the original mask/4 pulses are input to the data. means for inputting the sampling pulse as a shift clock to a first shift register and generating a plurality of mask pulses having different phases as output thereof; and a logical spear between the data sampling pulse and the reference V scan pulse. By using the output pulse obtained by taking and doing as a shift clock, shifting by the shift register of the 7 lane code detection pulse tg2, and converting the obtained output into data, the converted output is sent to the data selector. A mask/4 pulse generation circuit further comprising means for setting the data selector to select and derive one of the plurality of mask noculus.