JPS5848407A - Method of producing positive temperature coefficient porcelain semiconductor - Google Patents
Method of producing positive temperature coefficient porcelain semiconductorInfo
- Publication number
- JPS5848407A JPS5848407A JP14709181A JP14709181A JPS5848407A JP S5848407 A JPS5848407 A JP S5848407A JP 14709181 A JP14709181 A JP 14709181A JP 14709181 A JP14709181 A JP 14709181A JP S5848407 A JPS5848407 A JP S5848407A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- sheet
- temperature coefficient
- positive temperature
- producing positive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は正特性磁器半導体の製造方法に関する従来、正
特性磁器半導体には無電解メッキ法によるオーミック電
極の表面に金属粉末を含むペーストの塗布焼付によるカ
バー電極が形成しである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a positive characteristic ceramic semiconductor. Conventionally, a cover electrode is formed on a positive characteristic ceramic semiconductor by coating and baking a paste containing metal powder on the surface of an ohmic electrode using an electroless plating method. It is.
この半導体を加熱装置として用いた場合、その半導体の
熱を金属基板に良好に低木るために半導体と金属基板と
の間に熱伝導シートを介在させる方法が提案されている
。When this semiconductor is used as a heating device, a method has been proposed in which a heat conductive sheet is interposed between the semiconductor and the metal substrate in order to effectively transfer the heat of the semiconductor to the metal substrate.
このシートは一般には弾性をもった合成樹脂と金属粉末
との混合物が従来知られている。 。This sheet is generally known to be a mixture of elastic synthetic resin and metal powder. .
しかしながら、従来のシートはその製造が面倒であ、)
、しかも金属基板と半導体との間に介在(接着しない)
する構造のため、組付時にシートの位置がずれやすく、
従って組付性が非常に悪いという間at有している。However, conventional sheets are cumbersome to manufacture;
, and there is no adhesion between the metal substrate and the semiconductor.
Due to its structure, the seat position can easily shift during assembly.
Therefore, it has very poor assemblability.
そζで、本発明は上記の点に鑑み、熱伝導シートとして
グツファイト製のV−)(以下グツファイトV−Fと略
す)を用い、半導体の表面に前記ペー;L)を塗布した
後にその塗布部にグラファイトシー)を接着し、その後
に焼付けることによってカバー電極とグラファイトシー
トとを一体的に結合することにより、上記の諸問題を解
決しiうとするものである。Therefore, in view of the above points, the present invention uses Gutufite V-) (hereinafter referred to as Gutufite V-F) as a heat conductive sheet, and after applying the above P; L) to the surface of the semiconductor. The above-mentioned problems are attempted to be solved by bonding the cover electrode and the graphite sheet together by adhering a graphite sheet to the surface and then baking the cover electrode.
以下本発明を第1図の具体的実施例により詳細に説明す
る。本発明方法においては、まず従来公知の方法によっ
てTie、、BaC0,、、PbO,8i0□。The present invention will be explained in detail below with reference to a specific embodiment shown in FIG. In the method of the present invention, first, Tie, BaC0,, PbO,8i0□ is prepared by a conventionally known method.
Y、 0.等を混合して焼成したチタン酸バリウム系正
特性磁器半導体1を得る0この半導体lは例えば円板状
の形状を有している。半導体lは特定温度で抵抗値が急
増するキューリ一点をもっている。Y, 0. A barium titanate-based positive characteristic ceramic semiconductor 1 is obtained by mixing and firing the above semiconductors. This semiconductor 1 has, for example, a disk-like shape. The semiconductor 1 has a single Curie point where the resistance value increases rapidly at a specific temperature.
次いで、半導体1の両面を公知の方法で研摩して、その
研摩表面に無電解メッキ法によりNi製のオーミック電
極2を形成する。その後、このオーミック電極20表面
に、公知のムg粉末を含むペース)1150メツVユ〜
800メツシユのスクリーンにより印刷する。このペー
ス)面に、そのペーストが充分乾燥して固まらない内に
塗布後直ちに厚ミ0.1〜0.5flのグラファイトS
/ −) 4をそのペースト自身の粘着力により接着し
、その後全体を150℃〜500℃の温度で焼成し、上
記ぺ一ヌトを焼付ける。Next, both sides of the semiconductor 1 are polished by a known method, and ohmic electrodes 2 made of Ni are formed on the polished surfaces by electroless plating. Thereafter, the surface of this ohmic electrode 20 is coated with a paste containing a known mug powder.
Printed on an 800 mesh screen. Graphite S with a thickness of 0.1 to 0.5 fl is immediately applied to the surface of this paste before it dries sufficiently and hardens.
/-) 4 is adhered by the adhesive force of the paste itself, and then the whole is fired at a temperature of 150°C to 500°C to bake the above-mentioned paste.
これにより、ペース(はカバー電極3となり、かつグラ
ファイトシート4はこの[極3と一体的に結合し、剥離
することがなくなる。As a result, the paste becomes the cover electrode 3, and the graphite sheet 4 is integrally bonded to the electrode 3, and does not peel off.
なお、このグラファイトシート鳴の上面には金属基板6
が取付けられており、このグラファイトシート鳴を介し
て半導体lが基板6にばね等を用いて圧着しである。Note that a metal substrate 6 is provided on the top surface of this graphite sheet.
is attached, and the semiconductor 1 is crimped onto the substrate 6 using a spring or the like through this graphite sheet.
本発明は上述のごとく、グラファイトシート4がカバー
電極8と一体的に結合しているため、上記のように半導
体lを金属基板5に組付ける際にグラファイトシー)鳴
がずれることがなく、組付作業性が非常によくなる。ま
た、カバー電極8とグラファイトシート鳴とを結合する
のに接着剤を使用してシらず、カバー電極8の焼付工程
を利用−しているため、グラファイトシー)会の結合も
非常に簡単である。As described above, in the present invention, since the graphite sheet 4 is integrally combined with the cover electrode 8, the graphite sheet 4 does not shift when the semiconductor 1 is assembled to the metal substrate 5 as described above, and the assembly Workability is greatly improved. In addition, since the cover electrode 8 and the graphite sheet are bonded together using the baking process of the cover electrode 8 instead of using adhesive, bonding the graphite sheet is very easy. be.
次に、gg図〜第す図に実験結果を示す。Next, experimental results are shown in figures gg to s.
第8図は前記AgペーストのスクリーンFIIilJに
用いるスクリーンのメツシュサイズがガソリン混合気に
与える電力に与える影響を示している。ガソリン混合気
に与える電力(以下電力という)とは第19に示した構
成において、金属基板50表面に定温度、定流量のガソ
リン混合気をあてた時の半導体lが消費する電力である
。メツシュサイズが300メツシュ以上ではAgペース
トの厚みが充分でなく、グラフアイ【シート番が良好に
接着されず電力は低下する。一方、150メツシユ以下
であるとAgペーストの厚みが厚すぎて、熱伝導性が悪
化し、電力は減少する。FIG. 8 shows the influence of the mesh size of the screen used in the Ag paste screen FIIilJ on the electric power applied to the gasoline mixture. The electric power applied to the gasoline mixture (hereinafter referred to as electric power) is the electric power consumed by the semiconductor 1 when a gasoline mixture at a constant temperature and a constant flow rate is applied to the surface of the metal substrate 50 in the nineteenth configuration. If the mesh size is more than 300 meshes, the thickness of the Ag paste will not be sufficient, and the graph eye sheet will not adhere well and the power will decrease. On the other hand, if it is less than 150 meshes, the thickness of the Ag paste is too thick, resulting in poor thermal conductivity and reduced power.
第8図は半導体lとグラフアイ(シートるとの寸法差が
ショートに与える影響を示す。第3図のショーF率とは
、第1図の構成にて振動耐久を行ない、ショーF発生数
/全数とした。第3図の6寸法(半導体lの外縁とシー
)4の外縁との間の寸法)が0.6鱈より小さいと、シ
ミー1を発生する。Figure 8 shows the influence of the dimensional difference between the semiconductor l and the graph eye (sheet) on short circuits. /total number. If dimension 6 in FIG. 3 (dimension between the outer edge of semiconductor 1 and the outer edge of semiconductor 4) is smaller than 0.6, shimmy 1 occurs.
第4図はグラファイトシー)鳩の厚さが電力に与える影
響を示す。グラファイトシート4の厚さが0.1III
Iより薄い場合、半導体lおよび金属基板5の表面粗度
および歪に充分追従できず、電力が減少する。また、Q
jlgより厚い場合、熱伝導性が悪化し、電力が減少す
る。Figure 4 shows the effect of graphite thickness on power. The thickness of graphite sheet 4 is 0.1III
If it is thinner than I, it will not be able to sufficiently follow the surface roughness and strain of the semiconductor I and metal substrate 5, resulting in a decrease in power. Also, Q
If it is thicker than Jlg, the thermal conductivity will deteriorate and the power will decrease.
第5図はAgペーストの焼付温度が電力に与える影響を
示す。焼付温度が650℃より高いと、グラファイトシ
ー)番が分解してしまい、熱伝導性が悪化し、電力が減
少する。FIG. 5 shows the effect of baking temperature of Ag paste on power. If the baking temperature is higher than 650°C, the graphite carbon will decompose, resulting in poor thermal conductivity and reduced power.
また、焼付温度が150℃より低い温度で焼付は可能な
ムgペース)に使用できる材質はない。In addition, there is no material that can be used for mug paste, which can be baked at a baking temperature lower than 150°C.
次に、本発明の方法によ如得た半導体を採用した加熱装
置を第6.7,8図に示す。Next, a heating device employing a semiconductor obtained by the method of the present invention is shown in FIGS. 6.7 and 8.
第6図は金属基板5と底板8とによシ半導体1を収納し
たものであり、図中7はスプリングである。辷れは例え
ば内燃機関の吸気管のライザ壁に固定され、ライザヒー
タとして用いる。FIG. 6 shows a structure in which a semiconductor 1 is housed between a metal substrate 5 and a bottom plate 8, and 7 in the figure is a spring. The collar is fixed, for example, to the riser wall of the intake pipe of an internal combustion engine, and is used as a riser heater.
第7′図および第8図は円筒5,9の間に半導体lを配
設し、かつ正電極板6と絶縁材8を配設して複数のU字
形ばね7で半導体lを圧接したものである。これは例え
ば内燃機関の気化器と吸気管との間に配置して円筒5の
内側に燃料混合気を流す。7' and 8 show a structure in which a semiconductor 1 is arranged between cylinders 5 and 9, a positive electrode plate 6 and an insulating material 8 are arranged, and the semiconductor 1 is pressed by a plurality of U-shaped springs 7. It is. This is arranged, for example, between the carburetor and the intake pipe of an internal combustion engine, and allows the fuel mixture to flow inside the cylinder 5.
なお、本発明において、グラファイトシー)鳩は半導体
lおよび金属基板5の歪および表面粗度をその弾性力に
て吸収し、密着性の向上となり極めて良好な伝熱特性を
示す。グラファイトシー1番は電気伝導性も優れる。In the present invention, the graphite sheet absorbs the strain and surface roughness of the semiconductor 1 and the metal substrate 5 with its elastic force, improving adhesion and exhibiting extremely good heat transfer characteristics. Graphite Sea No. 1 also has excellent electrical conductivity.
第9図にその効果を示す。ムは本発明の例、は半導体お
よび金属基板を研摩し、両者を直接着した例、Cは研摩
せずに両者を直接圧着したを示す。Figure 9 shows the effect. 1 shows an example of the present invention, 1 shows an example in which a semiconductor and a metal substrate were polished and the two were directly bonded, and C shows an example in which the two were directly pressure bonded without polishing.
なお、本発明において、電極2.8の材質は述の実施例
に限らず、なんでもよい。In addition, in the present invention, the material of the electrode 2.8 is not limited to the above-mentioned embodiments, and any material may be used.
第1図は本発明により得た半導体を用いた釦装置を示す
断面図、第2図〜第6図は本発明の明に供する特性図、
第6図および第7図は末完によシ得た半導体を用いた加
熱装fflを示す断面第8図は第7図のA部拡大断面図
、第9図は本明の効果の説明に供する特性図である。
l・・・半導体、2.8・・・電極、4・・−グラフア
イシート。
代理人弁理士 岡 部 隆
第 11
第2図 第3図
@srj!A
ら
第 8 内
第9図FIG. 1 is a cross-sectional view showing a button device using a semiconductor obtained according to the present invention, and FIGS. 2 to 6 are characteristic diagrams for explaining the present invention.
6 and 7 are cross-sectional views showing a heating device ffl using a semiconductor that has been completely obtained. FIG. 8 is an enlarged cross-sectional view of section A in FIG. 7, and FIG. FIG. l...Semiconductor, 2.8...Electrode, 4...-Graph eye sheet. Representative Patent Attorney Takashi Okabe 11 Figure 2 Figure 3 @srj! Figure 9 of Figure 8
Claims (1)
成するとともに、その表面に金属粉末を含むペーストを
塗布焼付けてカバー電極を形成する際に、そのペースト
を塗布後にグラファイト製のシーFをそのペースト筐布
面に接着し、その後焼付けて前記シートを前記カバー電
極に一体的に結合する正特性磁器半導体の製造方法。Electrodes are formed on the surface of a PTC ceramic semiconductor by electroless plating, and a paste containing metal powder is applied and baked on the surface to form a cover electrode. A method of manufacturing a PTC porcelain semiconductor, which comprises bonding the sheet to a housing cloth surface and then baking it to integrally bond the sheet to the cover electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14709181A JPS5848407A (en) | 1981-09-17 | 1981-09-17 | Method of producing positive temperature coefficient porcelain semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14709181A JPS5848407A (en) | 1981-09-17 | 1981-09-17 | Method of producing positive temperature coefficient porcelain semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5848407A true JPS5848407A (en) | 1983-03-22 |
| JPS6161681B2 JPS6161681B2 (en) | 1986-12-26 |
Family
ID=15422266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14709181A Granted JPS5848407A (en) | 1981-09-17 | 1981-09-17 | Method of producing positive temperature coefficient porcelain semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848407A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60246693A (en) * | 1984-05-22 | 1985-12-06 | 三洋電機株式会社 | Hybrid integrated circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6431573U (en) * | 1987-08-19 | 1989-02-27 |
-
1981
- 1981-09-17 JP JP14709181A patent/JPS5848407A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60246693A (en) * | 1984-05-22 | 1985-12-06 | 三洋電機株式会社 | Hybrid integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6161681B2 (en) | 1986-12-26 |
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