JPS5853387B2 - Vector instruction processing method - Google Patents

Description

[Detailed description of the invention] (1) Field of application of the invention The present invention relates to a vector instruction processing method.

In particular, the present invention relates to an improvement in a vector instruction processing method that uses a data array vector as an operand in a data processing device that processes instruction words.

(2) Prior art The conventional vector instruction is A (I) = B (I) +
Array vectors such as C(I), A(I), B(I),
C(I) was stored on the storage device.

For this reason, it was not possible to process array vectors that use values directly as operands, such as A (I) - I + C (I).

(3) Object of the Invention The object of the present invention is to enable processing of array vectors that use values directly as operands in vector instruction processing.

(4) A device for determining whether an operand of a vector instruction directly generates a value based on a flag described in detail of the invention, and a device for directly generating the value of the operand.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 shows the configuration of a vector arithmetic processing device according to the present invention.

1 is an instruction control unit, 2 is an arithmetic unit, 3 is a storage control unit, 4 is a main memory, 5 is a vector instruction control unit, and 6 is a maintenance control unit.

We will now briefly describe the processing flow for ordinary commands other than vector commands.

The instruction words are stored in the main memory 4, and are taken into the instruction control unit 1 via the storage control unit 3.

Thereafter, the instruction control unit 1 decodes the instruction word and calculates the operand address, and the arithmetic unit 2 reads the operand and executes the operation of the instruction.

Reading of the operands takes place via the storage control unit 3.

In the case of a vector instruction, the instruction control unit 1 takes in the instruction word and decodes the instruction word in the same way as normal instruction word processing.

FIG. 2 shows the format of the vector instruction in this embodiment.

When the instruction code 102 is a vector instruction, a certain instruction code ('B4' in this embodiment) is given as in the case of a normal instruction word.

The general-purpose register number B2 for specifying a vector command indicates the number of a general-purpose register. The vector command part 110 of the contents of this general-purpose register and the vector command data 106 indicated by D2 are added by an adder 112 to obtain a vector command code 111. becomes.

This vector command code 111 indicates the type code of vector operation (addition, subtraction, multiplication, division, inner product operation, etc.).

The address vector command general register number R3 indicates a general register number, and the address of the address vector 114 is specified by the address 109 of the address vector of the contents of this general register.

Address vector 114 is comprised of three operand vector table addresses in this embodiment.

The three are vector table addresses for the first operand, the second operand, and the third operand.

In the example of FIG. 2, the second operand is illustrated, but the same applies to the first and third operands.

The address indicated in second operand vector table address 116 points to second operand vector table 118 .

The second operand vector full 118 is composed of a second operand vector address 119, an address increment value 120, and a plug 121.

Now, taking the case of A(I) = B(I)+C(I) as an example, A(I), B(I) j C
(I) correspond to the first, second, and third operands, respectively.

The second operand vector address 119 is the start address of the operand of array vector B(I) (i.e., B (
I) address).

Address increment value 120 is second operand B
(I) shows the pitch used.

Flag 121 is an important part of the invention.

In this embodiment, this flag 121 consists of 8 bits, one of which indicates whether the value is directly used as an operand.

In the case of the operation A(I)=I+C(I), by setting this bit to /1/, the value ■ can be directly used as an operand.

At this time, the operand vector address field 119 of the operand vector table 118 stores the initial value of the operand to be directly generated, and the address increment value field 120 stores the difference (increment value) between adjacent elements of the operand to be directly generated. ) is memorized.

For example, the operand "I" used in the operation A(I) = I + C (I+ is I = 1.2.3...
When generating by changing..., field 11
9120 are both set to 1.

FIG. 3 shows a more detailed block diagram of the vector instruction control unit 5, which is an important device of the present invention.

The second operand vector table 118 is read out to the arithmetic unit 2, and is transferred to the vector instruction control unit 5 via L14.

The operand vector address 119 is set in the register 205, the address increment value 120 is set in the register 203, and the flag 121 is set in the register 201.

Similarly, the third operand vector full address 11
7, the third operand vector table (not shown) is read out, and the operand vector address therein is read out.
Address increment values and flags are set in registers 206, 204, and 202, respectively.

The second operand buffer 209 and the third operand buffer 210 are used as buffers for pre-reading the second and third operands, respectively.

If the operands are stored in memory, such as array vectors B(I) and C(I), these operand buffers are used for pre-reading, and the second and third operands needed next are read. The signals are set in the registers 21L and 212, respectively, and sent to the arithmetic unit 5 via the interface device 213 and L5.

In this case, a known circuit (not shown) is used to read the second or third operand from the main memory 4.

For example, when reading the second operand from main memory, the operand vector address 119 of table 118
is sent as is to the main memory 4 as the address of the first vector element, and then an address increment value of 120 is repeatedly added to this operand vector address to create the address of the subsequent element. However, reading of the operand vector from the main memory 4 is performed only when the flag in the operand vector table is 00.

The vector thus read as the second operand is read ahead and stored in the buffer 209.

The same holds true when reading the third operand from the main memory 4; the third operand is pre-read and stored in the buffer 210.

Whether the operand is kept in memory or should be generated directly is determined by the register 201.2 for the second operand. For the third operand, register 202
Directed by the content of.

For example, for the second operand, if the specified bit of the register 201 is 1, the operand is to be directly generated, and the contents of the register 205, which stores the first element of the vector to be generated, are passed through the adder 207 and registered. 208 and further set in register 205.

Thereafter, the contents of register 205 and the contents of register 203 in which the increment value is stored are added, and the result is set in register 208 and then in register 205.

The addition is repeated in the same manner.

In this way, the elements of the vector operand to be directly generated are sequentially stored in the register 208.

On the other hand, the elements of the vector operand set in the register 208 are set in the register 211 via the line L203 every time this is set.

The contents of register 208 are transferred to register 20 via L203.
5 and is set in register 211.

The contents of the register 201 are sent out via L201, and the register 2110 is determined whether the human power to set it is L203 or not.
204.

The same applies to the third operand.

A flag is set in register 202, the contents of which determine whether the third operand is in memory or should be generated directly.

In the case of an operand to be directly generated, the first vector element to be generated for the third operand passes through adder 207 and is set in register 208 and then in register 206.

Thereafter, the contents of the register 204 containing the increment value are repeatedly added to the contents of the register 206 by the adder 207, and each time the result is set in the register 208 and then reset in the register 206.

In this way, the elements of the vector for the third operand to be directly generated are sequentially stored in the register 208.

On the other hand, the vector element set in the register 208 is set in the register 212 via the line L203 each time it is set.

The register 212 performs this setting when the flag of the register 202 is 1, and is controlled to set the output L205 from the buffer 210 when this flag is O.

Therefore, when the second operand is an operand that should be directly generated, as in the case of the vector operation A(I)-I +C(I), the vector element ■ sequentially generated in the register 208 is set in the register 211, and the main memory The vector element of the third operand read ahead from buffer 210 is set in register 212 from buffer 210 .

The next operand to be operated on is set in register 212 and register 211, and sent to operation unit 2 via L5.

The arithmetic unit 2 receives the operand sent via L5 when starting the arithmetic operation, and starts executing the arithmetic operation.

In the vector instruction control unit 5, when the arithmetic unit 2 starts executing an operation, the next operand is stored in the register 211.
, is set in the register 212.

(6) Summary As explained above, according to the present invention, A(I)−I
It is now possible to process vector instructions that directly generate operands such as +C(I).

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a data processing device showing an embodiment of the present invention, FIG. 2 is a schematic diagram of a vector instruction format in this embodiment, and FIG. 3 is a detailed explanation of an embodiment of the present invention. FIG. 2 is a more detailed block diagram.

Claims (1)

[Scope of Claims] 1. First means for storing a plurality of array vectors, first data representing the address of the first element of each of the plurality of array vectors, and second data representing an address increment.
and introduction data consisting of first data representing the first element of the array vector to be generated and second data representing the increment value between the elements; third means for reading the first and second set of data from the second means in response to a predetermined vector command; 2 is repeatedly added to generate a plurality of read addresses, and the first read address is generated based on the plurality of generated addresses.
fourth means for reading out the first array vector from the storage means; A vector instruction processing system comprising a fifth means for generating a vector, and a sixth means for executing an operation specified by the instruction on the first and second array vectors. 2. The second means is a means for storing a flag indicating whether each stored set of data corresponds to the array vector to be generated, along with each set of data, and the third means The means is means for reading two sets of data from the second means in response to the command, and the fourth and fifth means are configured to read out two sets of data from the second set of data in response to the command, and the fourth and fifth means are configured to read out two sets of data from the second set of data in response to the command. The vector instruction processing method according to the first item, wherein the first and second values are used as the first and second set of data.