JPS5854764A - Interface circuit - Google Patents
Interface circuitInfo
- Publication number
- JPS5854764A JPS5854764A JP56153259A JP15325981A JPS5854764A JP S5854764 A JPS5854764 A JP S5854764A JP 56153259 A JP56153259 A JP 56153259A JP 15325981 A JP15325981 A JP 15325981A JP S5854764 A JPS5854764 A JP S5854764A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- terminal
- logic
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 19
- 230000001934 delay Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
- H04L1/243—Testing correct operation by comparing a transmitted test signal with a locally generated replica at the transmitter, using a loop-back
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Bidirectional Digital Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は２線式回線を介して接続された自局装置と対局
装置との間のインタフェース回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit between a local station device and a game device connected via a two-wire line.
第１図は従来例を示す構成図である。２線式インタフェ
ース回路を有する自局装置１０１と、対局装置１０２と
が回線１０３を介して接続されている。FIG. 1 is a configuration diagram showing a conventional example. A local station device 101 having a two-wire interface circuit and a game device 102 are connected via a line 103.
まず、自局装置１０１から信号を対局装置１０２に送出
する場合について説明する。First, the case where a signal is sent from the own station device 101 to the game device 102 will be explained.
端子１から入力された送信信号は遅延回路１１に与えら
れると共に、端子２から出力信号として出力される。自
局装置１０１が端子ｌから送信信号を送出している間、
対局装置１０２は、送信されてきた信号をそのま捷返送
するので、自局装置１０１の端子３で受信される信号は
、送信信号と同じ論理信号とガる。端子３で受信した信
号は、論理積回路１３に与えられる。A transmission signal inputted from terminal 1 is given to delay circuit 11 and outputted from terminal 2 as an output signal. While the own station device 101 is sending out a transmission signal from terminal l,
Since the opposing station device 102 returns the transmitted signal as is, the signal received at the terminal 3 of the own station device 101 is the same logical signal as the transmitted signal. The signal received at the terminal 3 is given to the AND circuit 13.
また、遅延回路１１は、端子３から受信される信号が回
線１０３と対局装置１０２とをｂ’＆ 薊してくるため
遅延してい□るので、この遅延した遅延信号と送信信号
との時間差を補正するために、送信信号を遅延させる回
路であり、遅延させた信号を反転回路１２に与え、極性
を反転させて論理積回路１３に与える。Furthermore, since the signal received from the terminal 3 is delayed because it connects the line 103 and the game device 102, the delay circuit 11 corrects the time difference between this delayed signal and the transmitted signal. This is a circuit that delays the transmission signal for correction, and supplies the delayed signal to the inversion circuit 12, which inverts the polarity and supplies it to the AND circuit 13.
論理積回路１３では、前記端子３で受信された信号と反
転回路１２から出力された信号との論理積をとり、受は
側信号として端子４に送出する。The AND circuit 13 performs an AND operation on the signal received at the terminal 3 and the signal output from the inversion circuit 12, and sends it to the terminal 4 as a side signal.
端子１に与えられる送信信号が論理″′１″のときは、
反転回路１２の出力信号は、論理″０″となり端子３で
受信される信号は論理″１”であるから論理積回路１３
の出力信号は論理″０”となる。When the transmission signal given to terminal 1 is logic "'1",
The output signal of the inverting circuit 12 is logic "0" and the signal received at the terminal 3 is logic "1", so the AND circuit 13
The output signal of is a logic "0".
端子１に与えられる送信信号が論理ＩＴ Ｏ１１のとき
には、反転回路１２の出力信号は論理″′１″となり、
端子３で受信される信号は論理“０”であるから、論理
積回路１３の出力信号は論理″′０”となる。When the transmission signal applied to terminal 1 is logic IT O11, the output signal of inverting circuit 12 becomes logic "'1",
Since the signal received at the terminal 3 is a logic "0", the output signal of the AND circuit 13 is a logic "0".
上述のように、端子１からの送信信号が論理″′１″ま
たは論理６０”のいずれの場合においても、受は側信号
として、端子４から送出される信号は論理”Ｏ”全保持
し、送信信号が受は側信号に対して妨害することはない
。As mentioned above, regardless of whether the signal transmitted from terminal 1 is logic ``1'' or logic 60, the signal sent from terminal 4 is kept as a side signal, and the signal sent from terminal 4 is kept at logic ``O''. The transmitted signal does not interfere with the receiving signal.
次に対局装置１０２から信号が送出されてくる場合につ
いて説明する。Next, a case where a signal is sent from the game device 102 will be explained.
対局装置１０２から信号が送出されてくる場合、自局装
置の端子１に与える送信信号は論理″０″に固定してお
く。端子３での受信信号は回線１０３全介して、論理積
回路３に供給される。論理積回路１３では、端子３で受
信した信号と反転回路１２から出力された信号との論理
積分とり、受は側信号として端子４に送出する。ここで
、論理積回路は端子３で受信したイぎ号に対して、側ら
処理を行わず、そのま１受は側信号として端子４に送出
すると同等であり、送信信号は受は側信号に対して妨害
しない。When a signal is sent from the opposing device 102, the transmission signal applied to the terminal 1 of the local device is fixed at logic "0". The received signal at the terminal 3 is supplied to the AND circuit 3 through the entire line 103. The AND circuit 13 performs the logical integration of the signal received at the terminal 3 and the signal output from the inversion circuit 12, and sends the signal to the terminal 4 as a side signal. Here, the AND circuit does not process the signal received at terminal 3, and it is equivalent to sending it to terminal 4 as a side signal, and the transmission signal is the side signal. Do not interfere with
上述の従来回路構成では、遅延回路、反転回路および論
理積回路を用いているため部品点数が多くｈるという欠
点がある。The conventional circuit configuration described above has a disadvantage in that it requires a large number of parts because it uses a delay circuit, an inversion circuit, and an AND circuit.
本発明の目的は上述の欠点全除去したインタフェース回
路全提供することにある。SUMMARY OF THE INVENTION The object of the present invention is to provide a complete interface circuit which eliminates all of the above-mentioned drawbacks.
本発明の回路は２線式回線を介して接続された自局装置
と対局装置との間のインタフェース回路において、前記
自局装置から前記対局装置Ｈに送出する送信信号を分岐
し遅延させる遅延回路と、該遅延回路からの出力信号と
前記対局装置から信号との排他的論理和をとる排他的論
理和回路と全備えている。The circuit of the present invention is a delay circuit for branching and delaying a transmission signal sent from the local station device to the gaming device H in an interface circuit between the local station device and the game device H connected via a two-wire line. and an exclusive OR circuit that calculates the exclusive OR of the output signal from the delay circuit and the signal from the game device.
次に本発明について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.
第２図は本発明の一実施例を示す回路構成図である。FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention.
２線式インタフェース回路を有する自局装置１０１と、
対局装置１０３とが回線１０３を介して接続されている
。まず、自局装置１０１から器対局装置１０２に信号を
伝送する場合について説明する。A local station device 101 having a two-wire interface circuit;
A game device 103 is connected via a line 103. First, a case will be described in which a signal is transmitted from the own station device 101 to the player game device 102.
端子１に与えられた送信信号全遅延回路１１に与えると
共に端子２から出力信号として出力する。The transmission signal applied to terminal 1 is applied to the total delay circuit 11 and outputted from terminal 2 as an output signal.
２線式インタフェース回路を有する自局装置１０１が端
子１から送信信号を送出している間、対局装置１０２は
送信されて来た信号をそのまま自局装置に返送するので
、自局装置１０１の端子３で受信する信号は送信信号と
同じ論理信号となる。端子３で受信した信号は排他的論
理和回路１４に４夕られる。While the local device 101 having a two-wire interface circuit is sending out a transmission signal from terminal 1, the opposing device 102 returns the transmitted signal to the local device as is, so the terminal of the local device 101 The signal received at 3 is the same logical signal as the transmitted signal. The signal received at the terminal 3 is sent to an exclusive OR circuit 14.
＝５−
捷た、遅延回路１１は、端子３で受信した信号が回線１
０３と対局装置１０２とを通過してくるため遅延してい
るので、この遅延した遅延信号と送信信号との時間差を
補正するため、送信信号を遅延させる回路であり、遅延
させた信号を排他的論理和回路１４に出力する。=5- The delay circuit 11 switches the signal received at terminal 3 to line 1.
03 and the game device 102, so in order to correct the time difference between the delayed signal and the transmitted signal, this circuit delays the transmitted signal, and the delayed signal is exclusively transmitted. It is output to the OR circuit 14.
排他的論理和回路１４では、端子３で受信した信号と遅
延回路１１から出力された信号との排他的論理和をとり
、受は側信号として端子４に送出する。The exclusive OR circuit 14 performs an exclusive OR of the signal received at the terminal 3 and the signal output from the delay circuit 11, and sends it to the terminal 4 as a side signal.
端子ｌに与えられる送信信号が論理″１″のときには、
遅延回路１１の出力信号は論理″１″であり、端子３で
受信した信号も論理″１″であるから、排他的論理和回
路１４の出力信号は論理゛０″となる。When the transmission signal given to terminal l is logic "1",
Since the output signal of the delay circuit 11 is a logic "1" and the signal received at the terminal 3 is also a logic "1", the output signal of the exclusive OR circuit 14 is a logic "0".
端子１に与えられた送信信号が論理“ｌ Ｏｎのときに
は、遅延回路１１の出力信号は論理″Ｏ１１であり、端
子３で受信した信号も論理゛Ｏｎであるから、排他的論
理和回路１４の出力信号は論理″０″となる。When the transmission signal applied to the terminal 1 is the logic "l On", the output signal of the delay circuit 11 is the logic "O11", and the signal received at the terminal 3 is also the logic "On". The output signal becomes logic "0".
６−
上述のように、端子１からの送信信号が論理ｗ１″また
は論理″０”のいずれの場合においても、受は側信号と
して端子４から送出される信号は論理″０″を保持し、
送信信号が受は側信号に対して妨害することはない。6- As mentioned above, regardless of whether the transmission signal from terminal 1 is logic w1'' or logic ``0'', the signal sent from terminal 4 as a side signal of the receiver maintains logic ``0'';
The transmitted signal does not interfere with the receiving signal.
次に対局装置１０２から信号を自局装置に送出する場合
について説明する。Next, the case where a signal is sent from the game device 102 to the own device will be described.
対局装置１０２から信号が送１１４されてくる場合、自
局装置の端子１に与える送信信号は論理″′０″に固定
しておく。When a signal is sent 114 from the opposing device 102, the transmission signal applied to the terminal 1 of the own device is fixed at logic ``0''.
対局装置１０２から送出された信号は回線１０３回路１
１から出力された信号との排他的論理和をとり、受は側
信号として端子４に送出する。ここで、遅延回路１１か
ら出力された信号は論理″′０”であるので、排他的論
理和回路１４は端子３で受信１．た信号に対して何ら処
理を行わず、そのま１受は側信号として端子４に送出す
るのと同等であり、送信信号が受は側信号に対して妨害
することはない。The signal sent from the game device 102 is the line 103 circuit 1
The receiver performs an exclusive OR with the signal output from 1 and sends it to terminal 4 as a side signal. Here, since the signal output from the delay circuit 11 is logic "'0", the exclusive OR circuit 14 receives 1 . No processing is performed on the transmitted signal, and receiving the signal as it is is equivalent to sending it to the terminal 4 as a side signal, and the transmitted signal does not interfere with the side signal.
以上、本発明には回路構成の簡単化および部品点数の削
減全達成できるという効果がある。As described above, the present invention has the effect of simplifying the circuit configuration and reducing the number of parts.
第１図は従来回路の構成図および第２図は本発明の一実
施例を示す構成図である。
図において、
１・・・・・・送信信号端子、２・・・・・・出力信号
端子、３・・・・・・受信信号端子、４・・・・・・受
は側信号端子、１１・・・・・・遅延回路、１２・・・
・・・反転回路、１３・・・・・・論理積回路、１４・
・・・・・排他的論理和回路、１０１・・・・・・自局
装置、１０２・・・・・・対局装置、１０３・・・・・
・回線。FIG. 1 is a block diagram of a conventional circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1... Transmission signal terminal, 2... Output signal terminal, 3... Receiving signal terminal, 4... Receiving side signal terminal, 11 ...Delay circuit, 12...
...Inversion circuit, 13...AND circuit, 14.
...Exclusive OR circuit, 101... Own station device, 102... Opposing device, 103...
・Line.
Claims (1)
間のインタフェース回路において、前記自局装置から前
記対局装置に送出する送信信号を分岐し遅延させる遅延
回路と、該遅延回路からの出力信号と前記対局装置から
の信号との排他的論理和をとる排他的論理和回路とを備
えたことを特徴とするインタフェース。 υ[Scope of Claims] In an interface circuit between a local device and a game device connected via a two-wire line, a delay circuit that branches and delays a transmission signal sent from the local device to the game device. and an exclusive OR circuit that calculates the exclusive OR of the output signal from the delay circuit and the signal from the game device. υ
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56153259A JPS5854764A (en) | 1981-09-28 | 1981-09-28 | Interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56153259A JPS5854764A (en) | 1981-09-28 | 1981-09-28 | Interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5854764A true JPS5854764A (en) | 1983-03-31 |
Family
ID=15558537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56153259A Pending JPS5854764A (en) | 1981-09-28 | 1981-09-28 | Interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5854764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6338432U (en) * | 1986-08-26 | 1988-03-12 |
-
1981
- 1981-09-28 JP JP56153259A patent/JPS5854764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6338432U (en) * | 1986-08-26 | 1988-03-12 |
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