JPS6338432U - - Google Patents

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Publication number
JPS6338432U
JPS6338432U JP13040986U JP13040986U JPS6338432U JP S6338432 U JPS6338432 U JP S6338432U JP 13040986 U JP13040986 U JP 13040986U JP 13040986 U JP13040986 U JP 13040986U JP S6338432 U JPS6338432 U JP S6338432U
Authority
JP
Japan
Prior art keywords
circuit
signal
exclusive
transmission
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13040986U
Other languages
Japanese (ja)
Other versions
JPH0724832Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986130409U priority Critical patent/JPH0724832Y2/en
Publication of JPS6338432U publication Critical patent/JPS6338432U/ja
Application granted granted Critical
Publication of JPH0724832Y2 publication Critical patent/JPH0724832Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Bidirectional Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は第１図に示された実施例を動作させたと
きの信号の波形図、第３図は従来の送受信自動切
換回路の一例を示すブロツク図である。 １，１ａ……送信回路、２……ドライバ回路、
３，３ａ……レシーバ回路、４……排他的論理和
回路、５……受信クロツク生成回路、６……フリ
ツプフロツプ回路、７……受信回路、８……通信
路。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a signal waveform diagram when the embodiment shown in FIG. 1 is operated, and FIG. 3 is a block diagram showing an example of a conventional automatic transmission/reception switching circuit. 1, 1a...transmission circuit, 2...driver circuit,
3, 3a... Receiver circuit, 4... Exclusive OR circuit, 5... Reception clock generation circuit, 6... Flip-flop circuit, 7... Receiving circuit, 8... Communication path.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 通信路に対し、送信時に所定の送信データを出
力し、受信時に一定レベルの信号を出力する送信
回路と、この送信回路の出力信号と前記通信路か
らの信号との排他的論理和をとる排他的論理和回
路と、この排他的論理和回路の出力信号の特定の
信号周期に同期し所定の周波数のクロツク信号を
出力する受信クロツク生成回路と、前記排他的論
理和回路の出力信号と前記クロツク信号とを入力
し、この排他的論理和回路の出力信号に含まれて
いる受信データを取出すフリツプフロツプ回路と
を有することを特徴とする送受信自動切換回路。 A transmission circuit that outputs predetermined transmission data during transmission and a signal of a certain level during reception to a communication channel, and an exclusive circuit that takes an exclusive OR of the output signal of this transmission circuit and the signal from the communication channel. a reception clock generation circuit that outputs a clock signal of a predetermined frequency in synchronization with a specific signal period of the output signal of the exclusive OR circuit; and a flip-flop circuit which inputs a signal and extracts received data contained in the output signal of the exclusive OR circuit.
JP1986130409U 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit Expired - Lifetime JPH0724832Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986130409U JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986130409U JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Publications (2)

Publication Number Publication Date
JPS6338432U true JPS6338432U (en) 1988-03-12
JPH0724832Y2 JPH0724832Y2 (en) 1995-06-05

Family

ID=31027880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986130409U Expired - Lifetime JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Country Status (1)

Country Link
JP (1) JPH0724832Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854764A (en) * 1981-09-28 1983-03-31 Nec Corp Interface circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854764A (en) * 1981-09-28 1983-03-31 Nec Corp Interface circuit

Also Published As

Publication number Publication date
JPH0724832Y2 (en) 1995-06-05

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