JPS5856155A - Interruption processing system - Google Patents

Abstract

PURPOSE:To simplify a software and to reduce the overhead of a CPU by allowing a processor to accept an interruption request and to store corresponding interruption data in a main memory. CONSTITUTION:An interruption processing processor MPX15 rewrites a permit/ inhibition flag cell 142 into an access inhibition state to inhibit memory access from a CPU13 to a main memory 14, and also to fetch a top address from a top address cell 143 in the main memory 14. Then, the MPX15 uses the top address as an index to store interruption data in an interruption data area 145 in the main memory 14. Further, the MPX15 compares the contents of the cell 143 with those of a bottom address 144 to output an interruption signal to the CPU13 when the both coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt processing method for accepting interrupt requests generated by an interrupt generation module and processing interrupt data output from the interrupt generation module. .

In a system equipped with an interrupt generation module, an interrupt request generated by the interrupt generation module is generally notified to a central processing unit (hereinafter referred to as CPU) via an interrupt processing controller. Ru. A series of interrupt processing, from reception of an interrupt request to processing of interrupt data, is all performed by the CPU.

For this reason, in conventional systems, interrupt requests cannot be accepted when the CPU is in a busy state, resulting in problems such as a decrease in interrupt processing speed or the inconvenience that necessary interrupt processing is not executed. was there. Another drawback is that the software for interrupt processing is complicated.

The present invention has been made in view of the above circumstances, and its purpose is to:
An object of the present invention is to provide an interrupt processing method that reduces CPU overhead, simplifies interrupt processing software, and significantly increases interrupt processing speed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a system to which the present invention is applied.
), ATN, and ~ATN are interrupt signals indicating an interrupt request.

12 is an interrupt processing controller (hereinafter referred to as CNT). CNT 12 [INT 11, ~11n
The occurrence of an interrupt is detected according to the interrupt signal ATN -ATN output from the corresponding lNT11+~1.
Interrupt data is taken in from 1n.

After the CNT 12 receives the interrupt data,
The interrupt is notified to an interrupt processing processor 15, which will be described later. In this example, INT in CNT 12
The priority order of interrupt acceptance for 111 to 11n is determined by a daisy chain method.
The priority order is lNTl, . . . INT. Also, the priority order of interrupt signals is ATN, ,...AT
N, in that order.

13 is a CPU, 14 is a main memory, 15 is an interrupt processing processor (hereinafter referred to as MPX), and 16 is especially a CPU.
1 j, between main memory 14, main memory 14, MPX15
DMA (Dlrect M
memory Access) bus・Main memory 1
4 is the size self 4J, l' as shown in FIG.
It has an F-allowed/prefectural flag cell (hereinafter referred to as EI/bI cell) 142, a top address cell 143, a metom address cell J44, and an interrupt data area 1-5 for storing kZ and interrupt data. There is. size cell 1
Information indicating the size of the 41KFi interrupt data area 145 is set, and memory access permission (EI/1) I cell 142 for the interrupt data area 146 is set.
), information specifying prohibition (DI) is set.

The top address cell 143 has an interrupt data area 14
1. In this embodiment, the interrupt data area 145 is set to a FIFO (F'1rst) for interrupt data. In F
irst Out ) /47 is used as a fire.

The MPX 15 is activated by being notified of an interrupt from the CNT 12. It controls the storage of interrupt data stored in the MPX 15 in the interrupt data area 145, and outputs an interrupt signal ATNcPU to the CPU 13 as necessary. Furthermore, MPX 15 is capable of handling CNT after the above-mentioned processing is completed.
12, an interrupt enable signal ENA indicating permission for the next interrupt request is output.

On the other hand, the CPU 1 j is activated by an interrupt signal ATNOP U given from the MPX 15. Then, the CPU 13 extracts interrupt data from the interrupt data area 145 and performs predetermined processing based on the contents of the El/l)I cell 142 and the bottom address cell 143.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowcharts of FIGS. 3 and 4. 7'j For example, now, IN
An interrupt signal ATN is generated at T 11 ,
It is assumed that the occurrence of an interrupt is detected in the CNT 12. CNT I 2 Fi returns an interrupt approval signal in response to this detection result. INTJ 7° transfers its own device address to CNT 12 in response to this interrupt approval signal. CNT 12 receives the device address from INT 11 l and uses the device address to send it to INT 1.
When the CNT11 requests the interrupt r-event and the lNT11 transfers the interrupt data corresponding to the interrupt signal ATN, the CNT12 requests the corresponding interrupt r.
- The zero or more operating procedures for inputting data are performed according to known techniques.

When the CNT 12 finishes capturing the interrupt data, it notifies the MPX 15 of the interrupt.

As a result, MPX J s is activated and refers to El/DI cell 142 on main memory 14 . And EI/l
) If the I cell 142 indicates EI (memory access permission), MPX I & executes the interrupt acceptance process shown in the flowchart of FIG.

First, the MPX 15 connects the EI/I)I cell 142 to the DI(
Memory access prohibited) state and CPU IJ
While inhibiting memory access to the main memory 14 (its interrupt area 145), the top address is fetched from the top address cell 143 on the main memory 14 (Stella f83 J).

Next, MPX 15 uses this top address as an index to store the interrupt data transferred from INT 111 via CNT 12 in (interrupt data area 145 of) main memory 14 (Stella 7'5jj) . Next, the MPX 15 compares the contents of the top address cell 143 and the bottom address cell 144 (step S
! *If the top address and the tom address match, the MPX 15 outputs an interrupt signal ATNoPr1 to the CPU IJ in step 53.
4) Then, the content (dog address) of the top address cell 143 is incremented by 1 (step 535) to generate index data indicating the storage location of the next interrupt data.

On the other hand, if the top address and the I-tom address do not match, the MPX IE does not execute step 834 above and directly executes step 835.

The problem is that the interrupt 9 interrupt signal ATNo is sent to the CPU IJ.
, , if the CPU 1 j is in a busy state and the processing for the interrupt data stored in the interrupt data area 145 is not executed, CNT J j
Since interrupt data is stacked in the interrupt data area 145 in response to an interrupt notification from CPU J
By memorizing the fact that 3 is the output of the interrupt signal ATNoP, havk can be released from the busy state and can continuously process the stacked interrupt data. By doing this, unnecessary interrupts to the CPU 1j are prevented from occurring, and the overhead of the CPU 1J is reduced.

Next, the interrupt enable signal ENA is output to the MPX 15 ij CNT 12, and the EI/llll cell 142 is changed to the El state without writing (Stella 7"Sjg). The acceptance of an interrupt, which will be described later, enters a waiting state.

On the other hand, CPU J 3 is activated by an interrupt signal ATNoPU output from MPX 15. That is, the CPU 13 can recognize from the interrupt signals ATNo and U that interrupt data to be processed is stored in the interrupt data area 145. CPUJ
3 is not in the busy state, but refers to the E_I/I)I cell 142 when it is released from the dbusy state. and EI/l) If the I cell 142 indicates EI, then C
PU J 3 executes the interrupt data processing shown in chart 70 of FIG. First, CPU 13 is EI
/DI Rewrite I cell 142 to DI state and set MPX 1
5 from main memory 14 (interrupt area 146)
main memory 14 while prohibiting memory access to
Upper day? The gettom address is fetched from the tom address cell 144 (step 541). By the way, if the CPU 13 is not released from the busy state and cannot enter into interrupt data processing, the above-mentioned stellar fs41 will not be executed as is obvious, so the CPU J3 will not be able to process the EI/DI cell 142.
is never placed in the DI state. Want MPX J
5 is able to continue processing the interrupt reception described above in response to the side interrupt notification from the CNT 12, and the CPU I
CNT until J starts interrupt data processing
CPU I in which various interrupt data transferred via the JZ pipe are stacked in the interrupt data area.
When J finishes the execution of STETSUNO841, this STELLA f
The main memory 14 (interrupt data area 145) is accessed using the &tom address taken in by the execution of S41 as an index, and the corresponding interrupt data is read (step S42).6 Next, the CPU 13 uses the main memory 14 as an index. A predetermined process is executed based on the interrupt data read from the interrupt data area 145 (step 543), and then the bottom address cell 144
Add 1 to the contents (bottom address) (step 544
) Generates index data indicating where to read the next interrupt data. Next, the cru s s compares the contents of the top address cell 143 and the bottom address cell 144 (step 545), and if the top address and bottom address do not match, the CPo
Step 13 determines that there is still interrupt data to be processed, and repeats steps 842 to 844 until a match is detected. On the other hand, if the top address and bottom address match, the CPU 13 determines that there is no more interrupt data to process, and
Rewrite I cell 142 to EI state (step 846
). As a result, MPX 1B in the interrupt wait state
The side input reception shown in the flowchart τ of FIG. 3 can be processed.

As described in detail above, according to the interrupt processing method of the present invention, the following effects can be obtained.

■ The interrupt handling grosser accepts interrupt requests and stores the corresponding interrupt data in the main memory, so the CPU (Central Processing Unit) Fi simply retrieves the interrupt data from the main memory. It is only necessary to start the program and execute predetermined processing, which simplifies the software and reduces CPU overhead.

■ The above-mentioned operation of accepting an interrupt request and storing the interrupt data in the main memory is executed even when the CPU is in the Pinoy state and cannot process the interrupt data, so the CPU is released from the busy state. The interrupt processing speed is faster than the conventional method in which the interrupt request is accepted after the interrupt request is received.

■ During the period when the CPU cannot process the interrupt data, various interrupt data are stored (stacked) in the main memory as mentioned above, so once the CPU is interrupted, the interrupt data cannot be processed. C each time you store
The CPU can continuously process various interrupts without interrupting the PU. Therefore, the number of interrupts to the CPU can be reduced, and the side interrupt processing speed can be increased. This will further speed up the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a system to which the present invention is applied, FIG. 2 is a memory map of the main part of the main memory in the system, and FIGS. 3 and 4 are diagrams for explaining the operation. It is 70 1st. 111-11 ... Interrupt generation module (INT)
, 12... Interrupt processing controller (CNT)
, 13...Central processing unit (CPU), 24...Main memory, 15...Interrupt processing grosser (MPX),
142... Permission/prohibition flag cell (EI/DI cell)
, 143...Top address cell, 144...&)
program address cell, 145...interrupt data area. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (2)

[Claims] (1) In a system in which processing of interrupt data output from an interrupt generation module is performed by a central processing unit, a main memory having an interrupt data area in which the above-mentioned interrupt data is stored; It is activated in response to an interrupt request from the interrupt generation module, and controls the storage of interrupt data output from the interrupt generation module in the interrupt data area, and also issues interrupts to the central processing unit as necessary. The memory access enable/disable information is rewritten by the interrupt processing processor to be applied, this interrupt processing processor, and the above-mentioned central processing unit, and these interrupt processing processors and the central processing unit access the above-mentioned side interrupt data area at the same time. The central processing unit is activated in response to an interrupt from the interrupt processing processor, and is configured to include a permission flag cell and a prohibition flag cell for prohibiting the interrupt data area from being stored in the interrupt data area. An interrupt processing method characterized in that processing interrupt data is retrieved in the order in which it is stored and predetermined processing is performed. (2) The interrupt processing method according to claim 1, wherein the interrupt processing processor and the central processing unit rewrite the enable/prohibit 7 lag cells to a memory access disabled state upon startup.