JPS5856436U - hybrid integrated circuit structure - Google Patents

hybrid integrated circuit structure

Info

Publication number
JPS5856436U
JPS5856436U JP1981149671U JP14967181U JPS5856436U JP S5856436 U JPS5856436 U JP S5856436U JP 1981149671 U JP1981149671 U JP 1981149671U JP 14967181 U JP14967181 U JP 14967181U JP S5856436 U JPS5856436 U JP S5856436U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit structure
hybrid integrated
gold foil
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981149671U
Other languages
Japanese (ja)
Inventor
山口　光男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1981149671U priority Critical patent/JPS5856436U/en
Publication of JPS5856436U publication Critical patent/JPS5856436U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ、　　ｂは従来のグイボンディングを行う集積
回路の平面図および側面図、第２図は従来の他の集積回
路の平面図、第３図ａ、　　ｂは本考案の実施例の平面
図および側面図である。図において１・・・・・・部品
、２・・・・・・ろう材、３・・・・・・基板上のパタ
ーン、４・・・・・・ロー流れの処置のためのスリット
、５・・・・・・金箔、６・・・・・・基板、である。1A and 1B are plan and side views of an integrated circuit that performs conventional Gui bonding, FIG. 2 is a plan view of another conventional integrated circuit, and FIGS. 3A and 3B are plan views of an embodiment of the present invention. FIG. 3 is a diagram and a side view. In the figure, 1... parts, 2... brazing filler metal, 3... pattern on board, 4... slit for low flow treatment, 5 ...Gold foil, 6...Substrate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路用部品の接合面よりもやや大きい金箔を所定パ
ターン上に接合し、その金箔上に前記部品をボンディン
グして接合す゛ることを特徴とする混成集積回路構造。A hybrid integrated circuit structure characterized in that gold foil, which is slightly larger than the bonding surface of integrated circuit components, is bonded in a predetermined pattern, and the components are bonded onto the gold foil.
JP1981149671U 1981-10-08 1981-10-08 hybrid integrated circuit structure Pending JPS5856436U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981149671U JPS5856436U (en) 1981-10-08 1981-10-08 hybrid integrated circuit structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981149671U JPS5856436U (en) 1981-10-08 1981-10-08 hybrid integrated circuit structure

Publications (1)

Publication Number Publication Date
JPS5856436U true JPS5856436U (en) 1983-04-16

Family

ID=29942432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981149671U Pending JPS5856436U (en) 1981-10-08 1981-10-08 hybrid integrated circuit structure

Country Status (1)

Country Link
JP (1) JPS5856436U (en)

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