JPS5856471A - Compound semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a so-called comb-shaped structure in which a plurality of gate electrodes and source electrodes and drain electrodes are provided alternately between each of the gate electrodes. This invention relates to improvement of the 'di pole and wiring of a field effect transistor formed on a gallium arsenide (GtAs) substrate.

Semiconductor devices using compound semiconductors, especially gallium arsenide (GaAs), have excellent high-frequency characteristics and are suitable for high output due to various reasons such as their high electron mobility and the ability to form fine patterns. Because it is easy to implement, it is widely used as a power transistor for microwaves, and efforts are being made to further improve its degree of integration.

In prior art gallium arsenide (GaAa) based field effect transistors, an n-type gallium arsenide (GaAs) layer is epitaxially grown on a p-type insulating gallium arsenide (GaAs) substrate such as chrome (Or). This layer is used as a channel, and a method is often used in which a gate electrode, a source electrode, and a drain electrode are arranged on this layer, and the n-type epitaxial layer is mesa-etched from the region surrounding the thus formed device. However, those with mesa-etched steps are unsuitable for integration. Also, since it is more advantageous in terms of process than using epitaxial growth, ion implantation is used. It is desired to develop a planar type gallium arsenide (GaAs) based field effect transistor.

On the other hand, in order to increase the output power, a so-called comb-shaped structure in which a plurality of gate electrodes are provided and one source electrode and one drain electrode are arranged alternately between each gate electrode is advantageous. In such a structure, it is necessary to make the gate electrode width as small as possible. On the other hand, since each wiring, especially the source/drain wiring, requires a certain amount of current capacity, the width of each wiring, especially the source/drain wiring, must be increased to some extent. Therefore, there are cases where it is necessary to make the intervals between each wiring extremely narrow.

Semi-insulating gallium arsenide (GaAs), which is P-type with chromium (Or), etc., generally has a considerable amount of p-type and n-type impurities remaining1, so electric field conditions and temperature Depending on the conditions, these conductive impurities can cause dielectric breakdown, and the fact that the reliability of the dielectric strength between wires is questionable is an inherent drawback of conductor installation using gallium arsenide (GaAs). However, especially in the above-mentioned comb-shaped structure, this defect becomes obvious and becomes a fatal defect, and this defect has been solved in gallium arsenide (GaAa)-based field effect transistors having a comb-shaped structure. development was desired.

, the object of the present invention is to use semi-insulating gallium arsenide (GaA
a) In a planar type 1 field effect transistor formed using an n-type region (hereinafter referred to as an active layer) buried in the surface layer of the substrate and having a comb-type structure, the dielectric breakdown voltage between each wiring and the substrate is determined. The purpose is to provide an improved field effect transistor.In the above field effect transistor, at least one of the wirings connected to the gate electrode, the source electrode, and the drain electrode is made of the above gallium arsenide (GaAa). An n-type region (
Hereinafter, it is arranged on an n-type wiring layer (0), and the width of this wiring is narrower than the width of the n-type wiring layer. Next, the n-type impurity concentration of the n-type wiring layer is 10% of the n-type impurity concentration remaining in the gallium arsenide (GaAs) substrate.
The n-type impurity concentration V remaining in the substrate is usually 1014/α.
Since there is about 3 f, the n-type impurity concentration of the p-type layer for wiring is 1
It is desirable that the value is 0 ''/l:nr'' or more. Second, in order for the n-type layer for wiring to be effective, it is necessary that the thickness of the n-type layer be at least a certain value, but this minimum allowable thickness is the minimum thickness that can be formed on the substrate. It is recognized that fC tends to decrease as the impurity concentration of the n-type layer increases.On the other hand, when the impurity concentration of the n-type layer to be formed on the substrate is about 101s/an, the minimum allowable thickness is 10s/an.
There is 00Xr. Furthermore, if the impurity concentration of the n-type layer formed on the substrate is as high as about 1017/cy-'', the allowable minimum thickness will also be small, about 100 g.Thirdly, the n-type layer for wiring
It is safe to say that the difference between the width of the mold layer and the width of the corresponding wire is as large as 11%, but its minimum value increases depending on the voltage applied to that wire and is normally used. The IOV level is 1JIIn(
piece @0.5μm)? sufficient! However, approximately 1j2aun (1 μm on one side) is required for 100V#&.

Hereinafter, the process from the idea of the present invention to its embodiment will be explained. First, the inventors of the present invention have discovered that a silicon (silicon)
1) was ion-implanted to form an active layer, and this active layer was used to form a planar field effect transistor. Here, the source electrode, r rain iil! Wiring connected to the poles was arranged on a semi-insulating gallium arsenide (GaAa) substrate. For this prototype, the gate voltage was adjusted to increase the channel resistance, and even if the voltage between the source electrode and the P-rain bond was increased, the temperature of the active layer would not rise excessively. Source electrode/r-rain 'l'IN
A test was conducted in which the voltage between the two was gradually increased until dielectric breakdown occurred. What was observed in this breakdown test was that the point PJr where dielectric breakdown occurred was not on the active layer but on the semi-insulating substrate.

Therefore, we conducted the following test to reconfirm this phenomenon. That is, as shown in FIG. 1, first, a pair of metal layers 2 are formed on an insulating gallium arsenide (GaAa) substrate l with a distance x1 apart, and this distance X1 is set to 0.5 μm.
The relationship between the distance X1 and the dielectric breakdown voltage Vm was measured by changing the amount by .mu.m to .mu.m to cause dielectric breakdown between these metal layers 2, and the results shown in FIG. 2 were obtained. The figure shows the logarithm of the interval length x1 and the logarithm of the dielectric breakdown voltage VB. Next, as shown in FIG. 3, an insulating gallium arsenide (GaJks) substrate 1
A region 3 in which n-type impurities are selectively implanted into a partial region of the surface layer is formed at a distance of X, and a pair of metal layers 2 are formed thereon in ohmic contact. x
2 by varying the amount of 0.5 μm to (capital) μm, the metal layer 2
The relationship between the interval length x2 and the dielectric breakdown voltage Vn was measured by causing dielectric breakdown between the two, and the results shown in FIG. 4 were obtained. The figure shows the logarithm of interval length x2 and P! The logarithm of the edge breakdown voltage VB is shown.

As is clear from a comparison of Figures 2 and 4, it has been discovered that bioinsulating gallium arsenide (GaAs) substrates have unexpectedly poor dielectric strength. It has been confirmed that the reliability of the dielectric strength of semi-insulating compound semiconductors such as gallium arsenide (GaAθ) was incorrect.

Based on the above experimental results, when manufacturing a comb-type field effect transistor using semi-insulating gallium arsenide (GaAs) as a substrate, the wiring connected to each electrode, in particular,
If the distance between adjacent wirings is close or the first layer wiring arranged on the board (excluding the second and third layers arranged through a dielectric), etc. The above purpose can be achieved by forming an n-type region (an n-type layer for wiring) on the surface layer of a semi-insulating gallium arsenide (GaAs) substrate and placing wiring on top of the substrate. I concluded that it is possible.

Based on this conclusion, we repeated experiments to confirm this effect and confirmed the following facts. First, the n-type layer for wiring
Type impurity concentration and 1? Regarding the correlation with the effect on the edge resistance direction, the effect is significantly improved when the impurity concentration of the n-type wiring layer is 10 times the n-type impurity concentration remaining in the substrate, and when it is lower than that, the effect is significantly improved. It became clear that the effect was not necessarily significant with a difference of 1111 degrees. Since the residual n-type impurity concentration of the substrate is generally about IQ + 4 /crnll, the impurity concentration of the n-type wiring layer is preferably about 1015 /α3 or more. Second, regarding the correlation between the thickness of the n-type layer for wiring and the effect of improving dielectric strength, although this thickness is effective in improving the root dielectric strength, the impurity concentration of the n-type layer for wiring and the A correlation was observed, and it became clear that when the impurity concentration of the n-type wiring layer is high, the thickness of the n-type wiring layer can be thin.

Its effective minimum thickness is determined by the residual n-type impurity concentration of the substrate being 10
If the residual n-type impurity concentration of the substrate is about 101''/cIL3 or more, it is 1.00OA't%.Thirdly, the wiring n
Regarding the correlation between the difference between the width of the mold layer and the width of the corresponding wiring and the effect of improving dielectric strength, there is a correlation with the voltage applied to the wiring. It can be confirmed that there is a difference (approximately 0.5 μm on one side)
The effect of the present invention is approximately 100V!
In some cases, it was recognized that the difference in width must be about 2 μm (1 μm on each side).

A comb-type field effect transistor having the above configuration, that is, a gallium arsenide (Ga
A cross-sectional view and a plan view of a field-effect transistor of As) pace are shown in FIG. 5 and FIG. 6, respectively. In the figure, l is a semi-insulating gallium arsenide (05LA!+) substrate.
Reference numeral 4 indicates an active layer formed by ion-implanting n-type impurities such as silicon (Sl), followed by heat treatment. Reference numeral 5 denotes a source/drain region formed by further ion-implanting an n-type impurity such as silicon (Sl) and subjecting it to heat treatment. As shown in the plan view, this source/drain region is extended as it is to become the n-type wiring layer 51 which is the gist of the present invention. 6.7 are the source and drain electrodes -r! After depositing ants, gold/germanium (Mu-Go), etc., the source/drain electrodes are turned and heat treated to form ohmic contacts. It also extends onto the mold layer 51 to become source/drain wirings 61 and 71. Reference numeral 8 is formed by evaporating aluminum (AI) or the like with a Schottky rear gate electrode and then turning it. This gate electrode also extends to become a gate wiring 81, as shown in the plan view.

As explained above, according to the present invention, the solena type is formed using an n-type region, that is, an active layer, immediately provided on the surface layer of a semi-insulating gallium arsenide (GaAe) substrate.
In addition, it is possible to provide a field effect transistor having a comb-shaped structure in which the insulation strength between the wiring and the substrate is improved.

[Brief explanation of the drawing]

1 and 3 are cross-sectional views of the substrate used in experiments conducted to confirm the idea of the present invention, and FIGS.
The figure is a graph showing the results of the above experiment. FIG. 5.6 shows a cross-sectional view and a plan view, respectively, of a field effect transistor according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Metal layer, 3...Region into which n-type impurity is ion-implanted, "1...Distance between a pair of metal layers 2, x2...2 N-type Spacing between edges of regions, 4...
Active layer, 5... Source/drain region, 51... N-type layer for source/drain wiring, 6... Source electric body,
61... Source wiring, 7... Drain electrode, foot...
・Drain wiring, 8... Dirt electrode, 81... Gate wiring 0 Figure 2 LJ)g Xl f'Trr

Claims (1)

[Claims] (1) A plurality of gate electrodes are provided on an n-type region (active layer) buried in the surface layer of a semi-insulating arsenide diode IJJL substrate, and each of the plurality of gate electrodes is In a field effect transistor in which a source electrode and a drain electrode are provided alternately between the dirt electrode, the source electrode,
At least one of the wirings connected to the drain electrode is provided on an n-type region # (an n-type layer for wiring) buried in the surface layer of the semi-insulating gallium arsenide substrate, and the at least one wiring is connected to the drain electrode. A field effect transistor characterized in that its width is narrower than the width of an n-type layer for nuclear wiring. (2) The n-type impurity concentration of the wiring n-type layer is 10 times or more the n-type impurity concentration remaining in the bioinsulating gallium arsenide substrate. The field effect transistor described in 0(3) for the wiring n
The minimum allowable thickness of the mold layer decreases as the concentration of the n-type impurity for wiring formed on the semi-insulating gallium arsenide substrate increases, and when the concentration of the n-type impurity is 10" 10R.
Claim 1, characterized in that when the concentration of n-type impurities is 1017/crn3 or more, the minimum allowable thickness is 100X. Or the field effect transistor according to item 2. (4) The difference between the width of the n-type wiring layer and the width of the corresponding wiring increases as the maximum voltage applied to the corresponding wiring increases, and when the value of the maximum voltage is IOV, the difference is about 1 μm, , Meri, if the maximum voltage value is 100V, 2μ
Claim 1, characterized in that it varies by m.
The field effect transistor according to item 2 or 3.