JPS5869936U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5869936U
JPS5869936U JP1981165587U JP16558781U JPS5869936U JP S5869936 U JPS5869936 U JP S5869936U JP 1981165587 U JP1981165587 U JP 1981165587U JP 16558781 U JP16558781 U JP 16558781U JP S5869936 U JPS5869936 U JP S5869936U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor
semiconductor device
recorded
rows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981165587U
Other languages
English (en)
Inventor
荒井　眞幸
喜岡　隆一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1981165587U priority Critical patent/JPS5869936U/ja
Publication of JPS5869936U publication Critical patent/JPS5869936U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図および第２図は従来のポンディングパッドの配列
を持った半導体装置の平面図で部分的に詳細に示した図
であり、第３図および第４図はそれぞれ本考案の実施例
による半導体装置の平面図で部分的に詳細に示した図で
ある。 ｌ−ａ〜ｌ−ｄ・・・・・・半導体ベレット、２−ａ〜
２−小・・・・・ボンディング用パッド、３−ａ、　　
３−ｄ・・・・・・ボンディングワイヤ、４−ａ〜４−
ｃｌ・・・・・・リード。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体ペレットの辺に平行に複数列の電極取り出し用パ
    ッドを配したことを特徴とする半導体装置。
JP1981165587U 1981-11-06 1981-11-06 半導体装置 Pending JPS5869936U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981165587U JPS5869936U (ja) 1981-11-06 1981-11-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981165587U JPS5869936U (ja) 1981-11-06 1981-11-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS5869936U true JPS5869936U (ja) 1983-05-12

Family

ID=29957778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981165587U Pending JPS5869936U (ja) 1981-11-06 1981-11-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS5869936U (ja)

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