JPS5870552A - Preparation of semicondutor device - Google Patents

Abstract

PURPOSE:To shorten the ordered delivery term of semi-custom LSI's through destruction of ohmic connection between electrode and substrate by previously forming the electrode wirings on the element-formed semiconductor device surface and by implanting the O ion into the connection-unnecessary area. CONSTITUTION:The drain electrode windows 14, 14'... are formed and the wirings 12, 12'... are also formed. In response to the order, the surface is covered with the resist film 19 opening to the drain electrode window 14 which does not require wirings and the O<+> ion is implanted by providing wirings through the window 14. When th O<+> ion is implanted in the vicinity of interface between the wiring 12 and drain layer 14 by selecting an energy in accordance with thickness of wiring 12, the Si layer 15 and Al wiring combine with the oxygen O, resulting in the SiO2 and Al2O3. Thereby, connection with the wiring 12 is destroyed and the drain 2 of element T is isolated from the bit line B1. According to this structure, the ordered delivery term of semi-custom LSI such as mask ROM and gate array can be curtailed.

Description

[Detailed description of the invention]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semi-custom LSI such as a mask ROM or a gate array having different multi-connection wiring according to user's requirements. Semi-custom LSIs such as mask ROMs and gate arrays have different written information and circuit configurations depending on the user's requirements. To manufacture these devices, it is necessary to shorten the period from order receipt to delivery as much as possible. Therefore, semiconductor substrates on which the elements necessary to construct such devices are formed are prepared in advance, and the user A manufacturing method in which connection wiring is performed according to the required specifications is often used. The Shikashi-based manufacturing method requires two photo processes, including patterning of the opening of the tact window and electrode wiring based on the order specifications, after receiving the order and before delivery. Therefore, short delivery times for semi-custom LSIs are still not fully satisfactory. The purpose of the present invention is to further shorten the delivery time of semi-custom LSI, and in the present invention, electrode wiring is formed in advance on the surface of the semiconductor substrate after element formation, and electrode contacts that do not require connection are provided. The method is characterized by including a step of destroying the ohmic contact between the electrode and the semiconductor substrate by implanting oxygen ions into the electrode. An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example of manufacturing a mask ROM according to the present invention, and FIG. 1 is a circuit diagram showing the main parts of the memory cell connection of the mask ROM to be manufactured, and FIG. 2 corresponds to FIG. 1. A top view of the main part showing the pattern of the memory cell μ, FIG.
FIG. 2 is a cross-sectional view of essential parts taken along arrow 1-1 in the figure. In FIG. 1, T1 to T4 are 4 V constituting a memory cell.
jj: I-(Si,) MOS FET, Wx,
W, is a word line, B, , B, , B, is a bit line,
1.1' are respectively 81, MOS FET T, ,
The gate of T, 2.2/ is the drain, and 3.3' is the source, and the figure shows an example in which the drain 2 of T is not connected to the bit line Bl. T1 to T4 in Figure 2 are T□ to T4 in Figure 1 above, respectively.
11. Is it' the gate electrode wiring made of polycrystalline silicon? -Do line W□9w. 12.12', 12" corresponds to aluminum (AJ
) with different drain electrode wiring, bit line B,
, B, corresponds to , B,. Reference numeral 13 is a source wiring connected to a ground terminal, and serves as a source region in each element portion. 14.14' are contact windows of the drain 2.2', respectively. FIG. 3 is a cross-sectional view of a main part taken along arrow 1-1 in FIG. When T1 to T4 are n-channel ivMO8FFT, 81 substrate 16 is! Type, source region 16° drain region 1
5 and 15' correspond to the nm region. Reference numeral 17 denotes a field oxide film that defines the element region, and 18 an insulating film that covers the surface of the S1 substrate in the element region and the gate electrode wiring 11°11', and is, for example, a silicon dioxide (Sin) film. In the conventional manufacturing method, when the element formation is completed on the 81 substrate 16, that is, in the above-mentioned mask ROM, the gate electrode wiring 1 is placed on the field oxide film 17 in a constant element area.
1, 11', source and drain regions 13 and 15.
15', and the SiO□ film 18 is completely 18. After the order is received, a contact window for the drain electrode to be connected is opened according to the user's request.

[In the example of FIG. 1, the contact window 14 of T1 is not opened], the drain electric potential l1j
lk3 line 12.12'. It formed 12#. In contrast, in this embodiment, the contact windows 14, 14'... of all the drain electrodes are opened, and the electrode wiring 12,
12' and 12' are formed in advance. After receiving the order, the contact chamber 14 of the drain electrode that does not require connection, that is, the drain electrode of T1 in the example of FIG. 1, is selected according to the user's request.
Photoresist film 19 having an opening in the

[Indicated by broken lines in FIG. 3] is formed. Next, using this photoresist film 19 as a mask, oxygen ions (0+) are implanted by ion implantation.
The contact hole 14 is injected through the drain electrode wiring 12. At this time, it is important to implant oxygen ions (O+) near the interface between the drain electrode wiring 12 and the drain region 15. The thickness of the drain electrode wiring 12 is, for example, approximately 5 mm.
In the case of an A4 layer of ooo(A), the implantation energy may be approximately 150 [KeV]. Then, at the interface, Sl and Al combine with the injected oxygen to form S10. and Al5o. is formed. The amount of oxygen to be injected is I x 1017 [ar
If the value is 1 or more, the 8103 layer and the AJ, O, layer are formed over the entire area of the interface. Since both of these layers are insulating layers, the drain region 15 and the drain electrode wiring are formed in the contact window 14 part. 12 is severed, and as shown in FIG.
The drain 2 of the bit line B1 is isolated from the bit line B1. Thereafter, the photoresist film 19 is removed to complete the semiconductor device according to the present invention. In conventional manufacturing methods, two photo processes are required after receiving an order, and both require an etching process.
In this embodiment, the photo process only needs to be carried out once, and an etching process is not required as only the SiC photoresist film is formed. Therefore, in this embodiment, the process after receiving an order is shortened, and the work is significantly simplified. Note that the present invention is not limited to the above embodiment,
For example, in addition to a mask ROM, a CPU that includes a mask ROM
It can be used to manufacture various vegetation conductor devices such as semiconductor devices such as , gate arrays manufactured by the master slice method, etc. 9. According to the present invention, it is not limited to the drain electrode, but may also be the electrode of ξ, and the present invention is applicable not only to MO8FKT but also to various kinds of electrodes. It is not necessary to particularly explain that it is possible to manufacture a semiconductor device of. As explained above, according to the present invention, the delivery time of a Sisemi custom LSI can be significantly shortened.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining one embodiment of the present invention, in which FIG. 1 is a main circuit diagram showing the configuration of a semiconductor device to be manufactured in this embodiment, and FIG. FIG. 3 is a top view of the main part showing the pattern of the same part as the figure, and FIG. 3 is a cross-sectional view taken along the arrow line in FIG. In the figure, 1.1' is the gate), 2.2' is the drain,
3.3' is the source, 11.11' is the gate electrode wiring, 1
2, 12', 12# are drain electrode wirings, 13 is a source wiring including a source region, 14.14' is a contact window, 15.15' is a drain region, 16 is a semiconductor substrate,
18 is an insulating film, and 19 is a mask layer for ion implantation.

Claims (1)

[Claims] An element formation process is performed on the semiconductor substrate, and electrode wiring is formed to make contact with the surface of each formed element at a predetermined contact area, and then oxygen ions are injected into the desired contact area by penetrating the electrode wiring using an ion implantation method. A method for manufacturing a semiconductor device, the method comprising the step of implanting.