JPS5874054A - Semiconductor device - Google Patents

Abstract

PURPOSE:To perfectly prevent diffusion of metals into a Si substrate during thermal processing by forming the junction area in isolated manner between metal electrode and poly crystalline Si from the junction area of impurity layer. CONSTITUTION:An impurity layer 3 is formed on the one surface of Si substrate 1 with an oxide film 2 selective formed thereon used as the mask. Moreover, an oxide film 4 is formed, leaving a part of the layer 2 and a semiconductor layer, for example, a poly crystalline Si layer 5 is grown thereon. An impurity in the same conductivity type as the layer 3 is diffused into the layer 5, and thereafter the surface is thermally oxidized to have a low resistance. Thus, the layer 5 and layer 3 are electrically connected and simultaneously an oxide film 6 is formed. Then, a window is opened at the intermediate portion 6 of the film 5 being apart in lateral from the junction area between the layer 5 and layer 3, a metal electrode 7 is formed and a close contact with Si 5 is obtained. According to this structure, the junction area between the electrode 7 and Si 5 is isolated from the junction area of layer 2 and the electrode 7 and substrate 1 sandwiches an oxide film. Therefore, diffusion of metal into substrate 1 can be perfectly prevented resulting from the thermal processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device. Conventionally, the electrode wiring structure of a semiconductor element is a structure in which metal is deposited directly on a semiconductor substrate, which is effective for relatively deep PN junctions. In recent years, due to advances in semiconductor technology, very shallow P
It is possible to fabricate an N-junction (shallow junction type) by directly vapor depositing electrode metal on a semiconductor element having a leakage rate of 100% and performing hot porcelain. When the electrode metal spreads into the semiconductor, there are many accidents where it suddenly passes through the rigging part.The impurity diffusion layer changes, the layer resistance changes, the welding short circuits, etc. It has 0 flaws - eh. Recently, Iris xwt as something to compensate for these O flaws.

% of electrical distribution systems like this have been around for a long time.

That is, an impurity diffusion layer is formed selectively on the surface of the s/9 condenser substrate, and a layer of impurity diffusion is formed using the nine-layered layer 2 as a mask.Additionally, a part of the impurity diffusion layer s is left to form a layer 4 of the impurity diffusion layer. Then, a polycrystalline silicon layer is grown on the gold painting, and an impurity exhibiting the same isoelectricity as the impurity diffusion layer 1 is added to the diffusion layer lIb1I.
By carrying out the conversion to T, electrical conductivity between the polycrystalline silicon/@@ and the impurity diffusion layer s is obtained, and the formation of Klllll is caused. Thereafter, a hole is made in the hole, and a metal electrode lk1 is formed by vapor deposition. In other words, by sandwiching the above-mentioned 0 polycrystalline silicon 2 with the silicon 7 substrate and the metal electrode, the intention is to prevent metal diffusion into silicon, but even if it can be prevented to some extent, it cannot be completely prevented. However, electrical instability such as breakdown voltage and leakage often occurs in the device.

SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a semiconductor device that can substantially prevent diffusion of electrode metal into a semiconductor and has a versatile electrode wiring structure.

The features of the present invention are: - an impurity region of opposite conductivity type formed on one main surface of the semiconductor substrate of the doryuo; A semiconductor layer of opposite conductivity type for wiring, and a metal electrode connected to the semiconductor layer, wherein the connection portion between the metal electrode and the semiconductor layer is on the insulating film, and the semiconductor layer is connected to the semiconductor layer. The semiconductor device is located in the middle of the semiconductor device except for the vicinity of the ends.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a sectional view showing an embodiment of the present invention. An impurity layer 3 is formed using the oxide film selectively formed on one surface of the silicon substrate l as a mask. Further, an oxide film 4t is formed leaving a part of the impurity layer s, and then an oxide film 4t is formed over the entire surface from above. Half 4
The body layer 9, for example a polycrystalline silicon layer, is grown. This polycrystalline silicon layer is thermally oxidized after diffusing an impurity with the same conductivity ffi as the impurity layer 3 to make it low in resistance and to obtain electrical continuity between the polycrystalline silicon layer 5 and the impurity layer 3.
form. After that, polycrystalline silicon layer 5 and impurity J1
A hole is made in the oxide film 6 in the middle of the cedar rough layer 5 by photolithography and proboscising technology at a distance of more than 11 cm from the lateral wall from the 13O connection part. To obtain the shape o llk lI & 1) polycrystalline silicon ays and 0IIJ! 1ll
Make it t-11111. Regarding the metal electrode 10@@ mentioned above,
@, impurity layer 8, Ota Yoshizawa, multiple 1° crystal Vv coys, metal electrode 1, and OSS thin part overlap - m straight, # sailing ζ more than my - then the metal at the time of ripening Based on the thick layer that prevents O diffusion.

The 10th effect according to this Jll@ is that the metal electrode, polycrystalline silicon, and 01 groove are separated from the impurity layer O connection part and sp
D. The metal electrode and the semiconductor tsII [is a structure in which an oxide film is sandwiched between them, and %Ajk is rounded in 1, completely preventing the metal from diffusing into the silicon substrate during heating.

A circle, according to @5oyIh Kasha, a round where polycrystalline silicon is formed on the oxide film, polycrystalline silicon and electrode metal o * mw * are large amounts of money (take, electrode metal OR cut is small -
Well, the first thing to do is to obtain an electrode wiring structure with electrically reliable tactility and stability.

1 circle, the main @omso work is because the metal electrode is near the KIa mirror near the O end of the body, so there is no hole in the middle 11#CIII
! From %A, * 71 fk O number h Technique 11 and the structure like F-e, semiconductor layer 0J
llllll is a good tjjp conductor! 11 [@Run O Takashi Connect the ζO metal electrode to the W4 Takako region t) 114 Haruka electrode and ゐζ7-. 1llIl-
However, the same result can be obtained even if other semiconductors are used.

[Brief explanation of the drawing]

The first garden shows the remains of the conventional O semiconductor element Ot pole arrangement Wt-
Semiconductor device according to the present invention O actual example 011
111 is a cross-sectional view showing the wiring structure.
1 is a silicon substrate, 8 is a chemical layer, a is an impurity layer, 4 is a chemical reef, S is an ambiguous silicon layer containing the same amount of impurities as the impurity expansion Ik island 3, - Hiroki Chemical, 7 Is the money for the electrician m hh and the substitute Benranshi 8 tori cost

Claims (1)

[Claims] An impurity region of an opposite conductivity type formed on one main surface of a semiconductor substrate of one conductivity type; and an opposite conductivity type for wiring connected to the impurity region and extending over an insulating film provided on the main surface. a semiconductor layer, and a metal electrode connected to the semiconductor layer, and a connection portion between the metal electrode and the semiconductor layer is on the insulating film and in an intermediate portion of the semiconductor layer excluding the vicinity of an end. A semiconductor device characterized by: