JPS627703B2 - - Google Patents
Info
- Publication number
- JPS627703B2 JPS627703B2 JP59053244A JP5324484A JPS627703B2 JP S627703 B2 JPS627703 B2 JP S627703B2 JP 59053244 A JP59053244 A JP 59053244A JP 5324484 A JP5324484 A JP 5324484A JP S627703 B2 JPS627703 B2 JP S627703B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- opening
- insulating film
- semiconductor
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 本発明は、半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
従来、半導体素子の電極配線構造は、半導体基
板に直接金属を蒸着した構造で、比較的深いPN
接合には有効であつた。近年、半導体技術の進歩
により、非常に浅いPN接合(シヤロー・ジヤン
クシヨン型)の製作が可能となり、この浅いPN
接合を有する半導体素子に電極を形成する際に、
直接電極用金属を蒸着し、熱処理を行うと、この
電極用金属が半導体中に拡散されたり、接合部を
突き抜ける事故が多発する。このため、不純物拡
散層が変化し、層抵抗が変化するとか、接合が短
絡する等の欠点を有していた。 Conventionally, the electrode wiring structure of semiconductor devices is a structure in which metal is deposited directly on the semiconductor substrate, with relatively deep PN
It was effective for joining. In recent years, advances in semiconductor technology have made it possible to fabricate very shallow PN junctions (shallow junction type).
When forming electrodes on a semiconductor element having a junction,
When electrode metal is directly vapor-deposited and heat treated, accidents often occur in which the electrode metal diffuses into the semiconductor or penetrates through the joint. For this reason, the impurity diffusion layer changes, resulting in a change in layer resistance and short-circuiting of the junction.
これらの欠点を補うものとして最近第1図のよ
うな電極配線構造のものが提案されている。すな
わち、シリコン基板1の一表面に選択的に形成さ
れた酸化膜2をマスクとして不純物拡散層3を形
成する。さらに不純物拡散層3の一部を残して酸
化膜4を形成し、その全面に多結晶シリコン層を
成長させ、不純物拡散層3と同じ導電型を示す不
純物を拡散後熱酸化を行い、多結晶シリコン層5
と不純物拡散層3の電気的導通を得るとともに酸
化膜6を形成する。その後、酸化膜6を開孔し、
蒸着により金属電極7を形成する。すなわち上述
の多結晶シリコン5をシリコン基板と金属電極と
の間にはさむことにより、シリコンへの金属の拡
散を防ごうとする意図のものであるが、ある程度
は防止できても、完全ではなく、装置において耐
圧、リーク等の電気的不安定性を生ずることが少
なくなかつた。 In order to compensate for these drawbacks, an electrode wiring structure as shown in FIG. 1 has recently been proposed. That is, the impurity diffusion layer 3 is formed using the oxide film 2 selectively formed on one surface of the silicon substrate 1 as a mask. Furthermore, an oxide film 4 is formed leaving a part of the impurity diffusion layer 3, a polycrystalline silicon layer is grown on the entire surface, and after diffusing an impurity having the same conductivity type as the impurity diffusion layer 3, thermal oxidation is performed to form a polycrystalline silicon layer. silicon layer 5
Then, electrical continuity between the impurity diffusion layer 3 and the oxide film 6 is formed. After that, the oxide film 6 is opened,
A metal electrode 7 is formed by vapor deposition. That is, by sandwiching the above-mentioned polycrystalline silicon 5 between the silicon substrate and the metal electrode, it is intended to prevent the diffusion of metal into silicon, but even if it can be prevented to some extent, it is not perfect. Electrical instability such as breakdown voltage and leakage often occurred in the equipment.
本発明は、上記欠点を鑑み、実質的に電極用金
属の半導体内への拡散を防止できる電極配線構造
を備え、かの信頼性が高く、かつ配線の断線がな
く、フイールド領域の所定の絶縁分離が可能な集
積回路に適した半導体装置を提供することを目的
とする。 In view of the above-mentioned drawbacks, the present invention provides an electrode wiring structure that can substantially prevent the diffusion of electrode metal into the semiconductor, has high reliability, is free from disconnection of the wiring, and has a predetermined insulation structure in the field area. An object of the present invention is to provide a semiconductor device suitable for an integrated circuit that can be separated.
本発明の特徴は、半導体基板の一主表面に設け
られた第1の絶縁膜と、該第1の絶縁膜に設けら
れた第1の開口と、該第1の開口内の半導体基板
に設けられた不純物領域と、該第1の開口内より
該第1の絶縁膜上に延在せる第2の絶縁膜と、該
第1の開口内の該第2の絶縁膜の部分に設けられ
た第2の開口と、該不純物領域と同じ導電型を有
し該第2の開口を通して該不純物領域に接続しか
つ該第2の絶縁膜上を延在せる半導体層と、該第
2の開口より離間せる該半導体層の部分に接続せ
る金属層とを有する半導体装置にある。この半導
体層はその実質的全表面を絶縁被膜とくに熱酸化
膜で覆うことが好ましい。 The present invention is characterized by a first insulating film provided on one main surface of a semiconductor substrate, a first opening provided in the first insulating film, and a first insulating film provided in the semiconductor substrate within the first opening. a second insulating film extending from within the first opening onto the first insulating film; and a second insulating film provided in a portion of the second insulating film within the first opening. a second opening; a semiconductor layer having the same conductivity type as the impurity region and connected to the impurity region through the second opening and extending over the second insulating film; and a metal layer connected to the separated portions of the semiconductor layer. Preferably, substantially the entire surface of this semiconductor layer is covered with an insulating film, particularly a thermal oxide film.
以下、本発明を図面を参照に説明する。 Hereinafter, the present invention will be explained with reference to the drawings.
第2図は本発明の一実施例を示す断面図であ
る。シリコン基板1の一表面に選択的に形成され
た酸化膜2をマスクとして不純物層3を形成す
る。さらに不純物層3の一部を残して酸化膜4を
形成し、その上から全面に半導体層たとえば多結
晶シリコン層を成長させその中間部で不純物領域
3に接続させる。この多結晶シリコン層に対し、
不純物層3と同じ導電型の不純物を拡散後熱酸化
を行い、低抵抗層とし多結晶シリコン層5と不純
物層3の電気的導通を得るとともに酸化膜6を形
成する。その後フオトエツチング技術で酸化膜及
び多結晶シリコン層を選択的にエツチング除去
し、所定形状の多結晶シリコン層5およびその上
の熱酸化膜6を残余せしめる。この多結晶シリコ
ン層5の側面は続いて実施する高温熱酸化により
やはり熱酸化膜が形成されることとなる。その
後、多結晶シリコン層5と不純物層3の接続部よ
り横方向に数ミクロン以上離れたところの酸化膜
6にフオト・エツチング技術で開孔し、蒸着によ
り金属電極7を形成し、所定の形状を得る。金属
7をアロイすることにより多結晶シリコン5との
接触を強固にする。 FIG. 2 is a sectional view showing an embodiment of the present invention. Impurity layer 3 is formed using oxide film 2 selectively formed on one surface of silicon substrate 1 as a mask. Further, an oxide film 4 is formed leaving a part of the impurity layer 3, and a semiconductor layer, such as a polycrystalline silicon layer, is grown over the entire surface and connected to the impurity region 3 at an intermediate portion thereof. For this polycrystalline silicon layer,
After diffusing an impurity of the same conductivity type as impurity layer 3, thermal oxidation is performed to obtain electrical continuity between polycrystalline silicon layer 5 and impurity layer 3 as a low resistance layer, and to form oxide film 6. Thereafter, the oxide film and the polycrystalline silicon layer are selectively etched away using a photo-etching technique, leaving the polycrystalline silicon layer 5 in a predetermined shape and the thermal oxide film 6 thereon. A thermal oxide film is also formed on the side surface of this polycrystalline silicon layer 5 by the subsequent high-temperature thermal oxidation. Thereafter, a hole is formed in the oxide film 6 at a distance of several microns or more in the lateral direction from the connection between the polycrystalline silicon layer 5 and the impurity layer 3 using a photo-etching technique, and a metal electrode 7 is formed by vapor deposition, and a predetermined shape is formed. get. By alloying the metal 7, the contact with the polycrystalline silicon 5 is strengthened.
上述した金属電極7の位置に関しては、多結晶
シリコン5と不純物層3との接続部と、多結晶シ
リコン5と金属電極7との接続部が重ならない程
度、約数ミクロン以上離せば熱処理時の金属の拡
散を防ぐことができるという原理に基づく。 As for the position of the metal electrode 7 mentioned above, the connection between the polycrystalline silicon 5 and the impurity layer 3 and the connection between the polycrystalline silicon 5 and the metal electrode 7 should be separated by at least several microns so that they do not overlap during heat treatment. It is based on the principle that metal diffusion can be prevented.
本発明による第1の効果は、金属電極と多結晶
シリコンの接続部が不純物層の接続部から離れて
おり、金属電極と半導体基板とは酸化膜を間には
さむ構造となつているため、熱処理時に金属がシ
リコン基板に拡散することを完全に防げることで
ある。 The first effect of the present invention is that the connection between the metal electrode and polycrystalline silicon is separated from the connection between the impurity layer and the metal electrode and the semiconductor substrate have a structure in which an oxide film is sandwiched between them. In some cases, it is possible to completely prevent metal from diffusing into the silicon substrate.
また、本発明による第2の効果は、酸化膜上に
多結晶シリコンが形成されるため、多結晶シリコ
ンと電極金属の接触面積が大きくとれ、電極金属
の段切れが少ないため、電気的により確実な接触
性・安定性をもつ電極配線構造を得ることができ
る。そしてこの半導体層を熱酸化膜で覆つた場合
は、信頼性はさらに向上する。すなわち熱酸化膜
は気相成長の酸化膜に比べてその膜質も半導体層
への密着性も良好であり、又、その形成も容易で
あるからである。 In addition, the second effect of the present invention is that since polycrystalline silicon is formed on the oxide film, the contact area between the polycrystalline silicon and the electrode metal can be large, and there are fewer breaks in the electrode metal, making it more electrically reliable. An electrode wiring structure with excellent contact properties and stability can be obtained. When this semiconductor layer is covered with a thermal oxide film, reliability is further improved. That is, the thermal oxide film has better film quality and adhesion to the semiconductor layer than an oxide film grown in a vapor phase, and is also easier to form.
また、本発明による第3の効果は、第1の絶縁
膜と第2の絶縁膜とを併用したことである。これ
により第1の絶縁膜は、たとえば不純物領域の形
成のためのマスクとして用いかつフイールド領域
における所定の高い閾値電圧が得られるようにそ
の膜厚を定めることができる。一方、第2の絶縁
膜によつて不純物領域の所定の個所に半導体層と
の接続位置を定めることができ、又、その材質を
考慮することによつて絶縁膜の段部の角をなめら
かにすることができこれにより半導体層の断線を
なくすことができる。 Further, a third effect of the present invention is that the first insulating film and the second insulating film are used together. Thereby, the first insulating film can be used, for example, as a mask for forming an impurity region, and its film thickness can be determined so as to obtain a predetermined high threshold voltage in the field region. On the other hand, by using the second insulating film, it is possible to determine the connection position with the semiconductor layer at a predetermined location in the impurity region, and by considering the material of the second insulating film, the corner of the stepped part of the insulating film can be made smooth. This makes it possible to eliminate disconnections in the semiconductor layer.
なお、実施例では、シリコン基板につき説明し
たが、他の半導体を使用しても同様の効果が得ら
れる。 Although the embodiments have been described using a silicon substrate, similar effects can be obtained even if other semiconductors are used.
第1図は従来の半導体素子の電極配線構造を示
す断面図で、第2図は本発明による半導体素子の
電極配線構造を示し断面図である。
尚、図において、1はシリコン基板、2は酸化
膜、3は不純物層(領域)、4は酸化膜、5は不
純物拡散層3と同じ導電型の不純物を含む多結晶
シリコン層、6は酸化膜、7は電極用金属であ
る。
FIG. 1 is a sectional view showing the electrode wiring structure of a conventional semiconductor element, and FIG. 2 is a sectional view showing the electrode wiring structure of a semiconductor element according to the present invention. In the figure, 1 is a silicon substrate, 2 is an oxide film, 3 is an impurity layer (region), 4 is an oxide film, 5 is a polycrystalline silicon layer containing an impurity of the same conductivity type as the impurity diffusion layer 3, and 6 is an oxide film. The film 7 is a metal for electrodes.
Claims (1)
縁膜と、該第1の絶縁膜に設けられた第1の開口
と、該第1の開口内の半導体基板に設けられた不
純物領域と、該第1の開口内の半導体基板に被着
しかつ該第1の絶縁膜上に延在せる第2の絶縁膜
と、該第1の開口内の該第2の絶縁膜の個所に設
けられた第2の開口とを有し、これにより、該第
2の絶縁膜からなりかつ該第1の開口内に位置せ
る第1の部分と該第1および第2の絶縁膜からな
りかつ該第1の開口外に位置せる第2の部分とを
有した絶縁層を形成し、かつ、該第2の開口によ
つて該半導体基板の一主表面と該第2の絶縁膜に
おいて第1の段部を構成し、該絶縁層の第1の部
分と第2の部分とにより第2の段部を構成し、該
不純物領域と同じ導電型を有し該第2の開口を通
して該不純物領域に接続した半導体層が該第1の
段部から該絶縁層の第1の部分の上表面に被着し
さらに該第2の段部から該絶縁層の第2の部分の
上表面に被着して延在し、該半導体層は、該第1
の開口外であつて第1および第2の絶縁膜からな
る該絶縁層の第2の部分において、金属層と接続
したことを特徴とする半導体装置。1. A first insulating film provided on one main surface of a semiconductor substrate, a first opening provided in the first insulating film, and an impurity region provided in the semiconductor substrate within the first opening. , a second insulating film deposited on the semiconductor substrate in the first opening and extending over the first insulating film, and provided at a location of the second insulating film in the first opening. a second opening made of the second insulating film and located within the first opening; forming an insulating layer having a second portion located outside the first opening; The second step is formed by a first portion and a second portion of the insulating layer, and has the same conductivity type as the impurity region, and enters the impurity region through the second opening. A connected semiconductor layer is deposited from the first step onto the top surface of the first portion of the insulating layer and from the second step onto the top surface of the second portion of the insulating layer. the semiconductor layer extends from the first
1. A semiconductor device, wherein the semiconductor device is connected to a metal layer at a second portion of the insulating layer formed of the first and second insulating films outside the opening of the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59053244A JPS59229866A (en) | 1984-03-19 | 1984-03-19 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59053244A JPS59229866A (en) | 1984-03-19 | 1984-03-19 | semiconductor equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57049797A Division JPS57172763A (en) | 1982-03-27 | 1982-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59229866A JPS59229866A (en) | 1984-12-24 |
| JPS627703B2 true JPS627703B2 (en) | 1987-02-18 |
Family
ID=12937375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59053244A Granted JPS59229866A (en) | 1984-03-19 | 1984-03-19 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59229866A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4200753A1 (en) * | 1991-01-21 | 1992-07-30 | Mitsubishi Electric Corp | MOSFET with very short channel lengths - uses a multiple implant of dopant in source-drain regions to provide an abrupt, shallow box-shaped dopant profile to minimise punch through |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0254566A (en) * | 1988-08-18 | 1990-02-23 | Seiko Epson Corp | semiconductor equipment |
-
1984
- 1984-03-19 JP JP59053244A patent/JPS59229866A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4200753A1 (en) * | 1991-01-21 | 1992-07-30 | Mitsubishi Electric Corp | MOSFET with very short channel lengths - uses a multiple implant of dopant in source-drain regions to provide an abrupt, shallow box-shaped dopant profile to minimise punch through |
| DE4200753C2 (en) * | 1991-01-21 | 1996-09-26 | Mitsubishi Electric Corp | Semiconductor device with MOS field effect transistor and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59229866A (en) | 1984-12-24 |
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