JPS5875196A - Scanning pulse generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a nine-scan pulse generating circuit using a shift register.

(2) Prior Art A display device in which liquid crystal or other display elements are arranged in a matrix requires a drive circuit that generates a scanning pulse for sequentially scanning address lines and data lines.

As a scanning pulse generation circuit used in such a drive circuit, a multi-stage shift register S1 is used as shown in FIG.
.

Data/l system Din is input to the data input terminal of the first stage 81 of the shift register row 1 in which Sl...8n are connected in cascade.
By transferring the shift register row t8s→S, ...→an, each stage 81, 8B, ...B
From the output Q1 * Q of e=・Qn, as shown in FIG. ... A circuit that generates 2nt'' is known.

(3) Zhao point between conventional technology In FIG. 1, data/#rus Dim is black.

The signal is 11" only during one cycle of the master pulse CP, and during the other periods it is @Om during a snack while the shift register column l is performing a transfer operation. Generally speaking, a logic signal such as a shift register In the circuit, the power consumption increases significantly when the black and white pulses are input regardless of the presence or absence of data input.Therefore, in the scanning delta pulse generation circuit shown in Fig. 1, as the value of the pulse increases, the power consumption increases. , each stage 8 of shift register column 1
1eSlp...Even though the period in which a data full is applied to Sn and each of the outputs Qs - Qz - "Q% is 1 m is extremely short for one transfer cycle, the overall circuit Power consumption will increase significantly.

In order to solve this problem, the shift register array is divided into multiple blocks 31 and 32 as shown in Figure 3, and a clock pulse is applied to each of these blocks 31 and 32 for the period necessary for each block to perform a transfer operation. One possible method is to individually introduce the CP1e CPI. By setting K in this manner, the power consumption can be reduced to 1/the number of divided blocks of the shift register array.

However, in this case, in addition to the data/malus Din, it is necessary to introduce from the outside the same number of divided zeros, blacks, and mars as the number of splits, so if it is integrated into an integrated circuit, the number of lead-out pins will increase, which will reduce the cost and This is disadvantageous in terms of reliability.

(4) Purpose of the Invention The purpose of the present invention is to provide a low-cost and highly reliable scanning/malus generation circuit that consumes low power, has a minimum number of external connection terminals, and has low power consumption. .

(5) Summary of the Invention The scanning/malus generation circuit according to the present invention has a shift register array formed by connecting a plurality of stages of shift registers in cascade and dividing them into a plurality of processors. A single data signal is transferred to the clock signal 9 from the output of each stage of the shift register.
a control circuit that sequentially generates a scanning pulse in synchronization with the clock pulse, and the control circuit generates a clock pulse and the shift pulse in synchronization with the clock pulse. 1f of row
A control signal whose level is inverted every time it takes for the transfer operation to be completed is introduced, and each time the level of this control signal is inverted, the black, ri, and mars are distributed to each processor and ri in the shift register array. It is characterized by being composed of.

(6) Effects of the Invention According to the present invention, a shift register train is divided into a plurality of processors, and each processor has a clock/l system only during the period in which a scanning pulse is generated at each output. Therefore, power consumption can be effectively reduced.

Moreover, since the distribution of black and black pulses to each processor is done internally using control signals, the connection terminal between this scanning pulse generation circuit and the outside is basically one black and pulse input terminal. Only one control signal input terminal is required, and the number of terminals does not increase even if the number of divided blocks of the shift register array increases.The fact that the number of external connection terminals can be reduced is expanded, and when integrated circuits are integrated, the number of terminals does not increase. By reducing the number of external drawer bins, the area of the chia 1 can be reduced, which can greatly contribute to the cost reduction. Furthermore, reliability can be improved by reducing the number of external wirings.

(7) Embodiment of the invention FIG. 4 shows the configuration of a scanning A pulse generation circuit according to an embodiment of the invention, and FIG. 5 shows waveform diagrams of various parts. s””81
The circuit is divided into two circuits 41 and 42, and each circuit 41 and 42 is individually provided with a clock pulse CPtecP2 and a data clock D1tD from a control circuit 43.

The control circuit 43 is externally supplied with a control signal qS1 whose level is inverted every time each transfer operation of the CP, CP, and RI 47, 43 is completed, or the period of the scanning noise to be obtained at the output of each stage of the shift register train. A rectangular wave having the same period as T and a duty of 1/2 is introduced, and each time the level of the control signal CB is inverted, the protons, ri 41, 42, kutsumarus, and 1 digit are distributed.

That is, the control circuit 43 receives one of the inputs of the clock signal C8, the clock signal C8, and the clock signal C8, and sends it to the inverter 44.
Coconut Dart 45.46 with the inverted signal as the other input
and a shift register (Jl) with cp and cs as inputs.
'D-y ripfrog) 41, ANDr-4s and N0RI'-1. I/4
It has 9. Then, at the rising edge of C8o@O"→61" and the falling edge of "1"→"0", the first stage shift register 81 of 1 block 41°42 is transferred to "1" to S2+1.
``The level data bases D, , D, are supplied separately.

Also, during the period of CB="1.CB="0", professional, Ri4
Clock mother pulse CPt to each shift register of 1e42
*Supply CFx 'e respectively. As a result, the outputs Qs to Qn of each stage 81 to Bn of the shift register string,
Kuro, Ri・Mallus CP (Cpt *cp, )
Scans and mother pulses synchronized with are obtained sequentially.

According to this configuration, the number of shift registers in the shift register array that are in an active state and supplied with clock pulses is always 1/2 of all shift registers, and therefore power consumption is also approximately 1/2. In this case, it is also necessary to consider the power consumption of the control circuit 43;
If the number of block blocks is tens or more, the power consumption in the shift register array can be ignored.

In addition, since only two external connection terminals are required for inputting the clock signal CP and the control signal C8, the control circuit 4
Even considering the addition of 3, the increase in chip area when integrated circuit is extremely small, which is advantageous in terms of cost and design.

FIG. 6 shows another embodiment of the present invention, in which the shift register column t is divided into four blocks 61.degree.62.63.64. In addition, the waveform diagram of each part in Figure 6 is shown in Figure 7.
As shown in the figure. The control circuit 66 has a clock pulse CP and a duty cycle of 1/2 with a period T/2 (T is the period of the scanning pulse).
A control signal C8 consisting of a rectangular wave of
72, create each pro, RI 61 to 64, RI/R, CPt to CP4, and also inverter 66, shift register 62, AND dart 73.75 and N0R.
-f-) Create data/translations D1 to D4 for each professional program 74 and 76, and 61 to 64.

According to this embodiment, the power consumption of the control circuit 66 is ignored since it is always 1/4 of all the shift registers 81 to 8n that are in the impressed state when clock pulses are applied to the shift register array. Then, the total power consumption is reduced to about 174 when the shift register array is not divided into blocks. Further, although the number of divided blocks of the shift register array has increased to four, the number of connection terminals with the outside may be only two, as in the embodiment of FIG.

(8) Modification of the Invention In the embodiment, the number of divided blocks of the shift register array is 2 and 4.
Although the case has been described above, it goes without saying that the present invention can be similarly applied to the case of 3 or 5 or more.

In addition, in the embodiment, the data and mother pulses of each famic of the shift register array were created individually by the control circuit, but the final stage output terminal of the previous stage f o y ray and the first stage data pulse of the next stage fo It is also possible to connect directly to the input terminal and apply a data pulse every scan/dal cycle only to the first 1'f pulse input terminal of the shift register array.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the scanning/main pulse generation circuit, Fig. 2 is a waveform diagram of the scanning pulse to show its operation, and Fig. 3 is a scanning pulse waveform diagram in which the shift register row is divided into two blocks.
FIG. 4 is a basic configuration diagram of a scanning pulse generation circuit according to an embodiment of the present invention, FIG. 5 is a waveform diagram showing its operation, and FIG. 6 is a diagram of another embodiment of the present invention. FIG. 7 is a block diagram of the scanning pulse generating circuit according to the embodiment, and a waveform diagram showing its operation. 1...Shift register row, 31.3:jl, 4r. 42.61.6j1.61.64...Shift register column fayly, 43.65-...Control circuit, Sl
. S8. ...Sn...Shift register, CP p C
PReCP snow ecPH*cPa... Clock pulse, C8... Control signal, Di e DI s I
) s e D4 ・= data arm % Qt e
Qz e...Qt5...Scanning Hals output. Applicant's agent Patent attorney Takeshi Suzue 5111 Figure 3 Figure 61! ! W 61st! ! W 4

Claims (1)

[Claims] 91 data nodes are transferred through a shift register column consisting of a shift register column in which multiple stages of shift registers are connected in cascade and divided into a plurality of processors. and a control circuit that sequentially generates a scanning pulse synchronized with the clock pulse and the clock pulse from the output of each stage of the shift register, and the control circuit
A control signal whose level is inverted every time it takes for one block of the shift register array to complete the transfer operation is introduced into the clock pulse, and each time the level of this control signal is inverted, the level of the shift register array is inverted. A scanning pulse generation circuit featuring a pulse generator configured to distribute the pulses of each famitter clock I pulse.