JPS58767A - Detecting device of disconnection or short circuit - Google Patents
Detecting device of disconnection or short circuitInfo
- Publication number
- JPS58767A JPS58767A JP56098799A JP9879981A JPS58767A JP S58767 A JPS58767 A JP S58767A JP 56098799 A JP56098799 A JP 56098799A JP 9879981 A JP9879981 A JP 9879981A JP S58767 A JPS58767 A JP S58767A
- Authority
- JP
- Japan
- Prior art keywords
- test signal
- terminal
- circuit
- test
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 238000007689 inspection Methods 0.000 description 8
- 230000002950 deficient Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はプリント配線板等の断線または短絡。[Detailed description of the invention] The present invention prevents disconnections or short circuits in printed wiring boards, etc.
または断線及び短絡の検出装置に関する。Or it relates to a disconnection and short circuit detection device.
近年、プリント配線板に対し信頼性向上の要請が高くな
り従来の目視検査だけでは応じられなくなってきている
。そこで各種の検査装置が実用化されてきているが、さ
まざまな問題を抱えている。In recent years, there has been a growing demand for improved reliability of printed wiring boards, and conventional visual inspection alone is no longer sufficient to meet the demands. Various inspection devices have been put into practical use, but they have various problems.
例えばコンピー−ターを使用し良品と検f′一対象物と
の検査結果の比較を行なって判定する方法はどうしても
装置が複雑化し高価になってしまい。For example, a method of using a computer to compare the inspection results of a non-defective product and an object to be tested for determination inevitably requires complicated and expensive equipment.
さらに大量のデーター処理を行なうため検査に時間がか
かり1000ポイントを調べるのに1f4〜10秒程度
を要しまたデーターの読みとりミス等の計′1動作の恐
れがある。また分岐方式と呼ばれる装置においてはマト
リックスを組んだりピンボートを使用したりするため検
出ビンと検出装置との配線が非常に複雑で一般ユーザー
では配線不可能な場合すらあり、治具の価格及び納期に
も問題のある事が多い。又いずれの方式にしても検出は
ポイント別に行なわれることが多く不良部の表示とが。Furthermore, since a large amount of data is processed, inspection takes time, and it takes about 1f4 to 10 seconds to check 1000 points, and there is a risk of data reading errors and other errors. In addition, in devices called branching methods, the wiring between the detection bin and the detection device is extremely complicated because it uses a matrix or a pin board, and it may even be impossible for general users to do so, which can lead to significant jig costs and delivery times. There are also many problems. In addition, with either method, detection is often performed point by point, and defective parts are often displayed.
検出ビンと検出装置間の配線等が膨大な量となり煩雑に
なりがちである。The amount of wiring between the detection bin and the detection device is enormous and tends to be complicated.
本発明は以上の諸間門を改良するものであり以下一実施
例を第−図及び第二図により説明する。The present invention improves the above-described various gates, and one embodiment will be explained below with reference to FIGS.
第1図において検査対象回路が正常な場合にはテスト信
号出力端子1よりローレベルのテスト信号を送出すると
信号はピン2を介して検査対象回路3に流れ、さらにピ
ン4を介してテスト信号検出端子5に達する。従がって
テスト信号送出端子とテスト信号検出端子はいずれもロ
ーレベルで一致する。もしこの検査対象回路が断線して
いたとするとテスト信号検出端子にはローレベルノテス
ト信号が達せず、送出端子と検出端子のレベルは一致し
ない。従ってテスト信号送出端子にローレベルのテスト
信号が送出されている時、対をなすテスト信号検出端子
のレベルを判定すれば断線を検出することができる。In Figure 1, when the circuit under test is normal, a low level test signal is sent from the test signal output terminal 1, the signal flows to the circuit under test 3 via pin 2, and then the test signal is detected via pin 4. It reaches terminal 5. Therefore, the test signal sending terminal and the test signal detecting terminal both match at low level. If there is a disconnection in this circuit to be inspected, the low level test signal will not reach the test signal detection terminal, and the levels at the sending terminal and the detection terminal will not match. Therefore, when a low level test signal is being sent to the test signal sending terminal, a disconnection can be detected by determining the level of the paired test signal detection terminal.
又、複数のテスト信号出力端子に同時にはローレベルの
テスト信号を送出しないように制御してやれば、テスト
信号が送出されている検査対象回路以外は全てハイレベ
ルのはずである。もし検査対象回路と短絡している検査
対象外回路があったとすると、そのテスト信号検出端子
は当然ローレベルとなる。従ってテスト信号が送出され
ていないテスト信号検出端子すべてのレベルを調べ、ロ
ーレベルがあれば短絡とみなすことができる。Furthermore, if control is performed so that low-level test signals are not simultaneously sent to a plurality of test signal output terminals, all test signals other than the circuit to be inspected to which the test signals are being sent should be at high level. If there is a circuit not to be tested that is short-circuited to the circuit to be tested, its test signal detection terminal will naturally be at a low level. Therefore, the levels of all the test signal detection terminals to which no test signals are sent are checked, and if a low level is detected, it can be assumed that there is a short circuit.
ひき続き、第2図により検査対象回路が分岐している場
合について説明する。Continuing on, the case where the circuit to be tested is branched will be explained with reference to FIG.
検査対象回路が正常な場合、テスト信号出方端子1より
ローレベルのテスト信号を送出するとピン2.検査対象
回路3a、 3b、ピン4a、4bを介してオワゲート
素子乙に達する。オワゲート入力はすべてローレベルな
のでオワゲート出力もローレベルとなりテスト信号検出
端子5はローレベルとなる。もし検査対象回路3a、ま
たは3b、または3a及び6b両方が断線していた時、
オワゲート入力には一つ以上のハイレベル信号が入力さ
れるのでオワゲート出力はハイレベルとなりテスト信号
検出端子もハイレベルとなり、第1図で説明したと同様
の原理で断線を検出することが出来る。If the circuit under test is normal, when a low level test signal is sent from test signal output terminal 1, pin 2. It reaches the overgate element B via the circuit under test 3a, 3b and pins 4a, 4b. Since all of the OVER gate inputs are at a low level, the OVER gate output is also at a low level, and the test signal detection terminal 5 is at a low level. If the circuit under test 3a, 3b, or both 3a and 6b is disconnected,
Since one or more high level signals are input to the OVER gate input, the OVER gate output becomes a high level and the test signal detection terminal also becomes a high level, and a disconnection can be detected using the same principle as explained in FIG.
又、短絡についても第1図と同様の原理で検出出来る。Furthermore, short circuits can also be detected using the same principle as in FIG.
従って検査対象回路以上の検出回蕗の対を備え、テスト
信号を複数の検出回路に同時に送出することなく、すべ
ての検出回路に一度以上送出してやれば検査対象回路す
べてに対して断線または短絡の検査を行なうことが出来
る。Therefore, if you have more pairs of detection circuits than the circuit under test and send the test signal to all the detection circuits at least once without sending it to multiple detection circuits at the same time, you can test all the circuits under test for open circuits or short circuits. can be done.
以上のように本発明は簡単な回路構成による検査装置で
すみ安価に製作することが可能である。As described above, the present invention can be manufactured at low cost by using an inspection device with a simple circuit configuration.
又、テスト信号送出数をカウントし、不良検出時に検査
を一時停止しカウンター内容を表示してやれば不良箇所
が明確に判別出来る。In addition, by counting the number of test signals sent, temporarily stopping the inspection when a defect is detected, and displaying the contents of the counter, the defective location can be clearly identified.
なお本発明は、 TTLゲート素子を使用してテスト信
号の送出及び検出を行なうことが出来る。テスト信号検
出にヒステリシス特性を持つTTLゲート素子を使用し
た場合、正常か不良か判定される抵抗値は約3にΩと充
分実用になる値を示す。又静電破壊に対しても充分な耐
性があり、さらに検出速度が非常に高速で1,000回
路を100マイクロ秒程度で調べることが出来る。分岐
した検査対象回路に関しても検出ポイントを多入力オワ
素子に接続するだけでよいので、検査治具も簡単に製作
でき治具内に、オワ素子を設けた場合は治具と装置とを
接続するコネクター、配線が省略され少なくなるので安
価になる。多入力オワゲート素子は。Note that in the present invention, a TTL gate element can be used to transmit and detect a test signal. When a TTL gate element with hysteresis characteristics is used to detect a test signal, the resistance value for determining whether it is normal or defective is approximately 3.OMEGA., which is a value sufficient for practical use. It also has sufficient resistance to electrostatic damage, and has a very high detection speed, capable of examining 1,000 circuits in about 100 microseconds. Even for branched circuits to be tested, it is only necessary to connect the detection points to the multi-input power element, so the inspection jig can be easily manufactured.If the power element is provided in the jig, the jig and the device can be connected. The cost is reduced because connectors and wiring are omitted. Multi-input overgate device.
ワイヤードオワを利用してもよく、その場合配線はさら
に簡単になる。A wired wire may also be used, in which case the wiring will be even simpler.
テスト信号の制御は、フリップフロップを多段接続し直
列に入力、並列に出力してやれば簡単に実施できる。Test signals can be easily controlled by connecting flip-flops in multiple stages and inputting them in series and outputting them in parallel.
検査結果の判定には、エツジトリガータイプのフリップ
フロップを使用することが出来るので。Edge-trigger type flip-flops can be used to judge test results.
外乱ノイズに対して強い回路設計を行なうことが可能で
、さらにテスト信号出力端子からテスト信号検出端子に
いたる全ての部分の断線または短絡事故等は不良と判定
されるので確実な検査が行なわれる。It is possible to design a circuit that is resistant to disturbance noise, and since disconnections or short circuits in all parts from the test signal output terminal to the test signal detection terminal are determined to be defective, reliable inspection can be performed.
この様に本発明による断線または短絡の検出装置はシン
プルな動作原理と回路構成により安価に信頼度の高い検
査を、きわめて高速で安定して行なうことが出来る特徴
を有する。As described above, the disconnection or short-circuit detection device according to the present invention has the feature that it can perform highly reliable inspections at low cost and stably at extremely high speed due to its simple operating principle and circuit configuration.
第1図、第2図は本発明の一実施例を示す説明図である
。
1・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・テスト信号送出端子2.4.4a、 4
1) ・・・・・・・・検出ピン3.3a、 3b
・・・・・・検査対象回路5 ・・−・−・・・・・
・・・・・・・・・・ ・・・テスト信号検出端子6
・・・・・・・・・・・・・・ オワゲート素子特許出
願人 北斗制御株式会社
代表取締役 山 本 清
図面の浄書(内容に変更なし)
欠 1 薗
手続補正書(方式)
%式%[1
(
1、事件の表示 昭和56年特許願第98799号2
、発明の名称 断線または短絡の検出装置3、補正を
する者
事件との関係特許出願人
住所(居所)FIGS. 1 and 2 are explanatory diagrams showing one embodiment of the present invention. 1・・・・・・・・・・・・・・・・・・・・・・・・
......Test signal sending terminal 2.4.4a, 4
1) ......Detection pins 3.3a, 3b
・・・・・・Circuit to be tested 5 ・・・−・−・・・・
・・・・・・・・・・・・Test signal detection terminal 6
・・・・・・・・・・・・・・・ Owagate device patent applicant Representative director of Hokuto Controls Co., Ltd. Yamamoto Engraving of Kiyoshi drawing (no change in content) Missing 1 Written amendment of Sono procedure (method) % formula % [ 1 (1. Indication of the case 1982 Patent Application No. 98799 2
, Title of the invention Disconnection or short circuit detection device 3, Person making the amendment Address (residence) of the patent applicant related to the case
Claims (1)
からなる一対の検出回路を複数備えた。 断線または短絡の検出装置において、テスト信号を一個
のテスト信号送出端子から送出し、対をなす一個のテス
ト信号検出端子の状態、及び残り全てのテスト信号検出
端子の状應を判別する回路を備え、また複数の検出ポイ
ントからのテスト信号を論理演算する為のオワ機能を持
ったゲート素子を備え、その出力をテスト信号検出端子
に送る事により、検査対象物の断線及び短絡を検出する
装置。[Scope of Claims] A plurality of pairs of detection circuits each having one test signal sending terminal and one test signal detection terminal are provided. A disconnection or short-circuit detection device includes a circuit that sends a test signal from one test signal sending terminal and determines the state of one paired test signal detection terminal and the states of all remaining test signal detection terminals. , and a device that detects disconnections and short circuits in the object to be inspected by having a gate element with an output function for performing logical operations on test signals from multiple detection points, and sending the output to the test signal detection terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098799A JPS58767A (en) | 1981-06-24 | 1981-06-24 | Detecting device of disconnection or short circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098799A JPS58767A (en) | 1981-06-24 | 1981-06-24 | Detecting device of disconnection or short circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58767A true JPS58767A (en) | 1983-01-05 |
Family
ID=14229393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56098799A Pending JPS58767A (en) | 1981-06-24 | 1981-06-24 | Detecting device of disconnection or short circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58767A (en) |
-
1981
- 1981-06-24 JP JP56098799A patent/JPS58767A/en active Pending
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