JPS5877085A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize the independent writing to an optional bit of plural data groups, by holding the writing control signals at a data bit selection signal latching circuit and controlling the writing data which is fed later with the output of a latching circuit. CONSTITUTION:An address ADD indicating a data storing area is applied, and a chip selection signal CS and writing signal WE have a fall respectively. Thus the data bit selection signals added to data input/output terminals 1/01-1/04 are latched to a latching circuit 8. Now it is supposed that the terminal 1/03 is equal to a bit which requires the writing, and accordingly the bit is set at ''1'' with a time band (a) and ''0'' with other time bands. When the signals CS and WE have a rise respectively, the data is latched. Then only the data of 1/03 is written at a time band (b), and other data become to the read out state. In such way, the independent writing is possible to an optional bit of the writing control signals comprising plural data groups.

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention Regarding read/write control methods in memory For this reason, it is desired to develop a memory with excellent performance. (3) Prior art and problems The data of a semiconductor memory expansion having multiple data input terminals or data input/output terminals is desired. It is not possible to independently perform a read/write operation on any bit of a group; in particular, during a write operation, it is necessary to read and rewrite a series of data bits. Therefore, e.g. If you want to change only one bit among the bits, the entire series of 4m bits stored at address 9 is rewritten, and not only the 1 bit that needs to be changed but also all the remaining bits are rewritten, which saves processing time. (4) Purpose of the Invention This invention has the disadvantage that it is impossible to measure the shortening of data.
The object of the present invention is to provide a semiconductor memory provided with a means for independently writing data into the semiconductor memory.

(5) Structure of the Invention The present invention provides a data bit selection signal latch circuit inside the memory to detect a data bit selection signal which is a write control signal added to a normal data input terminal or a data input/output terminal. It is possible to write to any bit independently.

(6) Embodiment of the Invention FIG. 1 shows the write operation timing of the invention. As an example, the memory has four data input/output terminals, that is, four data bits. When the address ADD indicating the data storage address is given, the chip select signal C8 for selecting a chip falls, and the write signal WE falls, the data input terminals l101. l102. l103.
The data bit selection signal added to l104 is latched. For example, if l103 is a bit that requires writing and the others are bits that do not, then only l103 has a time period of 11'' indicated by a, and the others are W''0101. Chisui. In this case 1101
．． l102. l104 is in the read state during the time period indicated by b), and only 1703 has a data bit selection signal of '''1.
1 to indicate that only l103 is a write request.
For example, the data at address n of Memineri M is 18 l102. l103. If you want to set the data group whose data is mt+s for l104 to @01 only for engineering 103, l101. l102. l104 has ″″ respectively.
0′.

@l'' and @1# are read and rewritten to '1''Ai''0'K at address n of memory M for l103.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and is similar to FIG. 1; for example, it shows a case where there are four data input/output terminals. The row address signal line is decoded by the row decoder 1, and the column address signal is decoded by the ram decoder 4 and passes through the column input/output circuit 4 to select the address of the memory array 2.
Data that needs to be written is added to 10S, and other data are
Input/output 11111 child l101. l102. l104
If writing is not necessary, the chip select signal is applied to the CB terminal and the write signal is applied to the WE terminal in the sequence shown in FIG.
The circuit 6 and the input data control circuit 3 are controlled. Only the data input/output terminal l103 is turned on in the sequence shown in Figure 1. The 〇 indicating that the data pit selection signal is @1m is latched by the falling edge of the write signal of the corresponding w, x, y, and zrcwg terminals. do. As mentioned above, since only l103 is "11", the data bit selection signal latch circuit 8
The terminal Q of company Y is set to "1" and O is set to @O, the gate 11 of the data controller 5 is opened and the write data is sent to the input data control circuit 3. The input data control circuit 3 controls the Y/Q terminal output of the data bit selection signal latch circuit 8 and the above-mentioned - jitter control! Under the control of the 11 circuit 7, data is written to the address corresponding to the 1 cough data child 103.

When the data output cover v7A6 data bit selection signal latch circuit 80Y has mutual terminal @Om, its gate 15
◎ W, X of data bit selection signal latch circuit 8.

2 is a data input/output terminal l101. l102. l104 sets the terminal Q of each ninth terminal of @0# to @O'KQt''''1''. Therefore, data person Kapuffer 5's game) 9.1
0.12 is closed to prevent data transfer, and the gates 13, 14, and 16 of the data output pad 7a are opened.
Under the control of the four-thick control circuit 7, the read state is entered.

The above explanation refers to writing to the data input/output terminal 3, and the same applies to other terminals], and if data bit selection signals are simultaneously superimposed on two or more terminals, multiple terminals corresponding to the superimposed terminals Similarly to 4, bits can be written.

(7) As described in detail, the present invention is a means for superimposing a data bit selection signal, which is a write control signal, on a data input terminal or a data input/output terminal, and for checking the data bit selection signal. A data bit selection signal l!P circuit is provided,
By latching the data bit selection signal using the falling edge of the write signal, which has not been used in the past, it is possible to write any bit of the data group), and perform the read operations necessary for the write operation. It is possible to reduce the memory access time of the information processing system by making the operation unnecessary, and the effect is great.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the write operation timing of the present invention.
The figure is a vertical diagram of a circuit showing an embodiment of the present invention. In the figure, 1 is a 11 decoder and 2 memory cell array. 3 is an input data control circuit, and 4 is a column input/output circuit. And Kotsum Dep, -da, 5 is data human cover v7a. 6 is a data output pad 7a, and 7 is a p-thick control circuit. 8 is a data bit selection signal latch circuit.

Claims (1)

[Claims] In a semiconductor memory having a plurality of data input terminals or data input/output terminals, a data bit selection signal 2-bit circuit is provided to control write data that is inputted prior to write data from the data input terminal or data input/output terminal. The signal is held in the armpit latch circuit, and then the input write data is controlled by the latch circuit output.It is possible to independently perform a write operation on any pin (K) of a plurality of data groups from ζAK. Semiconductor memory is characterized by the ability to