JPS5879751A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To increase the latch-up resistance by a method wherein P well is formed by means of double diffusion of boron and aluminium. CONSTITUTION:P type region (P well) is formed on n type silicon substrate 1 in an island form. On the p well, n channel MOS transistor 3 comprising source and drain 7, 8 and gate electrode 5 is formed while on the n type substrate 1, p channel MOS transistor 4 comprising source and drain 9, 10 and gate electrode 6 is formed. p<+> type region 11 and n<+> type region 12 are respectively a contact region. The p well 2 is formed by the first p type region 15 comprising boron introduced and the second region 16 comprising aluminium introduced deeper than the region 15. Through these procedures, a latch-up may be prevented without changing a threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION 11) Technical Field of the Invention The present invention relates to a complementary semiconductor device, and more particularly to the structure of a complementary semiconductor device having an MIS structure capable of increasing rough bulge strength.

(2) Prior Art and Problems In complementary semiconductor devices having an MIS structure, one of the challenges has long been to increase the latch-up resistance.

Figure 1 is a cross-sectional view of the main parts of a silicon complementary MO3 field effect transistor (hereinafter abbreviated as CMO3FET), which is an example of a complementary semiconductor device with an MIS structure. A cross section is schematically shown.

In the figure, 1 is an n-type silicon (St) substrate, 2 is a p-type region formed in an island shape (hereinafter abbreviated as p-well), and 3 and 4 are an n-channel type element and a p-channel type element, respectively. 5.6 is a gate electrode, 7.8 is a source and drain region of an n-channel type device, both of which are n-type regions, 9.10 is a source and drain region of a p-channel type device, both of which are p-type regions, 11 is a contact region of a p-well, and the p+ type region 12 is a contact region of an n-type substrate, which is an a-type region.

FIG. 2 is a circuit diagram showing the inverter circuit in correspondence with FIG. 1.

The OMO3FET configured in this manner has a p-type source region 9. N-type Si substrate 1. There are a pnp parasitic bipolar transistor constituted by a p-well region 2 and an npn parasitic transistor constituted by an n-type Si substrate 1° p-well region 2 and an n-type source region 7. However, when the CMO3FET is normally used, these parasitic transistors do not operate because measures are taken to consider the bias applied to each part. However, if large noise is applied to the input/output terminals or the power supply, the parasitic transistors may operate.

FIG. 3 is a circuit diagram equivalently showing the above parasitic transistor, and 13. Reference numerals 14 indicate the pnp type and npn type parasitic transistors, respectively. As seen in the figure, once these parasitic transistors start operating, the collector current of one becomes the base current of the other, reinforcing each other's operations, and the state may become fixed. This is a phenomenon called latch-up, and when the element is in this state, the element is destroyed due to heat generated by the large current flowing inside.

Therefore, in complementary Mis FETs such as 0MO3FETs, it is important to make the latch amplifier less likely to occur, that is, to increase the latch-up resistance.

It is known that in order to increase the latch-up resistance, it is possible, in principle, to increase the impurity concentration of the p-well, or to increase the depth of the p-well (the thickness in the vertical direction in the figure). However, in the former method, the threshold voltage of the n-channel element depends on the surface concentration of the p-well, so there is a restriction that the impurity concentration of the p-well cannot be made extremely high.

In addition, the latter is boron (
Since B) has a small diffusion coefficient, it takes a long time to carry out deep diffusion using this method.

If aluminum (AIl) with a large diffusion coefficient is used, p
Although it is easy to form a deep well, heat treatment in the device formation process that follows after the formation of the p-well may cause
Since l is further diffused and the surface concentration of the p-well changes, it becomes extremely difficult to control the threshold voltage of the device, which is affected by the surface concentration of the p-well.

Due to these difficulties, it cannot be said that any previous attempts to increase the latch-up strength have achieved sufficient results.

(3) Object of the Invention An object of the present invention is to provide an improved structure of a complementary Mis FET that can solve the above-mentioned problems and increase the launch-up resistance.

(4) Structure of the Invention The present invention is characterized in that it has a p-type region formed in the form of an island on the surface of an n-type semiconductor substrate, and an n-channel field effect transistor element is formed on the surface of the island-like p-type region. In the complementary semiconductor device having an MIS structure in which a p-channel field effect transistor element is formed on the surface of the n-type semiconductor substrate, the island-shaped p-type region has a first p-type region doped with boron.
The second p-type region is composed of a type region and a second p-type region in which aluminum is introduced deeper than the first p-type region.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a curve diagram showing the impurity concentration distribution in the depth direction of the p-well, which is a main part of an embodiment of the complementary MIS FET according to the present invention. Since the schematic cross-sectional shape of the element of this embodiment is the same as that shown in FIG. 1, one embodiment will be described below with reference to FIG.

In FIG. 4, the horizontal axis represents depth and the vertical axis represents impurity concentration, and curve 15. 16 are boron (B) and aluminum (A) in the depth direction in the p-well 2 of the device of this embodiment, respectively.
Curve 17 shows the p-type impurity concentration distribution of the sum of both.

As seen in the figure, the device of this embodiment has a p-well 2 with a first layer made of boron (B) diffused to a depth of about 3 [μm], and aluminum' (A J ) made of e.g. and a second layer diffused to a depth of approximately 9 μm. Such a p-well 2 is formed by forming a silicon dioxide (Sin) film on the surface of an n-type substrate l having a resistivity of about 4 [Ω-1], for example, with the p-well 2 forming region as an opening. It can be formed by introducing B and A1 into the surface of the opening of the n-type substrate 2 using an ion implantation method as a mask, and then diffusing them at a temperature of about 1200 ('C) for about 3 hours. When ion-implanting the above B and AJ, the implantation energy and dose are as follows: B is approximately 60 (keν), 4 X IQ12 (all
-2), and AN is approximately 100 (keV),
3 X 10I2 (CIQ-2), then if you perform the diffusion as described above, B and All will each be approximately 3
The p-well 2 is diffused to a depth of (+um)', 9 (, um) and has an impurity concentration distribution as shown in FIG. In this case, the surface concentration of AI is one order of magnitude lower than the surface concentration of B.

By forming the p-well 2 into such a structure, the surface concentration can be controlled independently by the diffusion of B, and the depth can be controlled independently by the diffusion of A1. Therefore, in the CMO3FET of this embodiment, the p-well 2 has a predetermined surface concentration determined by the required threshold voltage and a desired depth. Since the latch-up resistance can be increased, the latch-up resistance is increased, and other electrical characteristics are not affected at all.

As described above, the present invention provides a complementary semiconductor device having an MIS structure that can increase latch-up resistance.

[Brief explanation of the drawing]

Figure 1 shows a complementary MI configured as an inverter circuit.
2 is a circuit diagram of the inverter circuit described above, FIG. 3 is an equivalent circuit diagram for explaining the parasitic transistor action of the device shown in FIG. 1, and FIG. 4 is a diagram illustrating the present invention. FIG. 3 is a curve diagram showing the impurity concentration distribution of the p-well in one example.

Claims (1)

[Claims] A p-type region is formed in the form of an island on the surface of the n-type semiconductor substrate, an n-channel field effect transistor element is formed on the surface of the island-like p-type region, and a p-channel field effect transistor element is formed on the surface of the n-type semiconductor substrate. MIS made up of elements
In a complementary semiconductor device having a structure, the island-shaped p-type region includes a first p-type region formed by introducing boron;
A complementary semiconductor device characterized in that it is composed of a second p-type region formed by introducing aluminum deeper than the first p-type region.