JPS5882575A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5882575A
JPS5882575A JP56180479A JP18047981A JPS5882575A JP S5882575 A JPS5882575 A JP S5882575A JP 56180479 A JP56180479 A JP 56180479A JP 18047981 A JP18047981 A JP 18047981A JP S5882575 A JPS5882575 A JP S5882575A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
semiconductor
layer
insulating
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56180479A
Other languages
Japanese (ja)
Other versions
JPS6233741B2 (en
Inventor
Takao Yamamoto
山本 ▼‖ひ▼男
Hideo Sugiura
杉浦 英雄
Zeio Kamimura
税男 上村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56180479A priority Critical patent/JPS5882575A/en
Publication of JPS5882575A publication Critical patent/JPS5882575A/en
Publication of JPS6233741B2 publication Critical patent/JPS6233741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/80FETs having rectifying junction gate electrodes

Landscapes

  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce floating capacity of the device by a method wherein a III-V group compound semiconductor made to have the semiinsulating property by adding impurities to form a deep level is used for a substrate, and out of a metamorphosed layer generated on the surface by a heat treatment, only the surface layer part is removed to be made as the substrate for a Schottky junction type FET. CONSTITUTION:The heat treatment is performed at 800 deg.C for about 5hr to the GaAs substrate 1 made to have the semiinsulating property by adding Cr to form the deep level, added Cr is made to diffuse toward the surface of the substrate 1, and the thermally metamorphosed layer 4 consisting of the low resistance surface layer part 2 scarcely containing Cr or containing scanty Cr even when Cr is contained, and the surface layer part 3 containing a large quantity of Cr and positioning on the surface thereof, is made to be generated. Then the surface layer part 3 is removed using an aqueous solution of sulfuric acid, the low resistance surface layer part 2 is left as the surface layer part 5, a source electrode 7 and a drain electrode 8 consisting of an AuGe alloy are formed thereon, an Al gate electrode 9 is provided between them, and the Schottky junction 10 is made to be generated between the electrode 9 thereof and the surface layer part 5.

Description

【発明の詳細な説明】 本発明は、半絶縁性半導体基板本体の表面側に低抵抗半
導体層を形成してなる構成の半導体基板を用いて所要の
半導体素子を形成してなる半導体装置及びその製法の改
良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which required semiconductor elements are formed using a semiconductor substrate having a structure in which a low resistance semiconductor layer is formed on the surface side of a semi-insulating semiconductor substrate body, and a semiconductor device thereof. Concerning improvements in manufacturing methods.

萌梳半導体装置は、その半導体基板が半絶縁性半導体基
板本体を用いた半導体基板であるので、その半導体基板
を用いて形成された複数の半導体素子を互に分離されて
なる。ものとして構成することが出来ること、各半導体
素子を浮遊容置の小なるものとして構成することが出来
ること等の特做を有するものである。
Since the semiconductor device uses a semi-insulating semiconductor substrate as its semiconductor substrate, a plurality of semiconductor elements formed using the semiconductor substrate are separated from each other. It has the characteristics that it can be constructed as a single object, and that each semiconductor element can be constructed as a small floating container.

所で知■植半導体装置及びその製法−こ於ては、その半
導体素子が高性能を有する為に、その半導体基板を楕成
せる低抵抗半導体層に、大なる電子移動度を有すること
、所要の大なる厚さを有すること、小なる比抵抗を有す
ること等が要求されるものである。
In order for the semiconductor device to have high performance, it is necessary to have a high electron mobility in the low-resistance semiconductor layer that can form the semiconductor substrate. It is required to have a large thickness, a small specific resistance, etc.

然し乍ら、従来の斯種半導体装置及びその製法に於ては
、上述せる髪求事項を十分満足し得るものでないという
欠点を有していた。
However, conventional semiconductor devices of this type and methods of manufacturing the same have the drawback of not being able to fully satisfy the above-mentioned requirements.

依って本発明は上述せる欠点のない新規な斯種半導体装
置及びその製法を提案せんとするもので、以下詳述する
所より明らかとなるであろう。
Therefore, the present invention aims to propose a novel semiconductor device of this type and a method for manufacturing the same that does not have the above-mentioned drawbacks, which will become clear from the detailed description below.

本発明による半導体装置の一例及びその製法の一例を、
第1図を伴なってその製法の一例を以って述べるに、深
い準位を形成する不純物Orの松加により半1#1#性
化されてなるGaAs  でなる■−V族化合物半導体
基板本体1を予め用意する(第1図A)。
An example of a semiconductor device according to the present invention and an example of its manufacturing method are as follows:
To describe an example of the manufacturing method with reference to FIG. 1, a ■-V group compound semiconductor substrate made of GaAs which has been made semi-1#1# by using the impurity Or that forms a deep level. The main body 1 is prepared in advance (FIG. 1A).

而してその■−■族化合物半導体基板本体1に対する、
例えば800℃、例えは5時間の熱処理を、例えば1気
圧のA3  蒸気圧を有する雰囲気にてなす。然るとき
は、半導体基板本体1の表面IIIに於て、それに添加
されている不純物としてのOr が半導体基板本体1の
表面に向って拡散乃至輸送し、この為第1図Bに示す如
く半導体基板本体1の表面側に、不純物としてのcr 
 を殆んど含有していないか含有しているとしても熱処
理前に比し格段的に少ない菫しか含有していない、従っ
て低抵抗を呈している部2と、その部2上のOr  を
熱処理前に比し多量に含有している表向部3とを有する
熱変性NlI4が形成されるものである。尚この場合熱
変性層4は、これを部2をしてα2μm%表面部6をし
てα1μmの厚さを有するものとして形成し得るもので
ある。
Therefore, for the ■-■ group compound semiconductor substrate body 1,
For example, the heat treatment is performed at 800° C. for 5 hours in an atmosphere having an A3 vapor pressure of 1 atm, for example. In such a case, Or as an impurity added to the surface III of the semiconductor substrate body 1 diffuses or is transported toward the surface of the semiconductor substrate body 1, and as a result, the semiconductor as shown in FIG. Cr as an impurity on the surface side of the substrate body 1
The part 2 that contains almost no violet, or even if it does contain much less violet than before the heat treatment, and therefore exhibits low resistance, and the Or on that part 2 are heat treated. Heat-denatured NlI4 is formed which has a larger amount of NlI4 in the surface portion 3 than before. In this case, the heat-denatured layer 4 can be formed to have a thickness of α2 μm% and a surface portion 6 of α1 μm.

次に、斯く半導体基板本体1に対する熱処理により、そ
の表面側に熱変性層4を形成して后、その熱変性層4に
対する例えば硫酸系水溶液を用いたエツチング処理によ
り、熱変性層4の表面側を少くとも表面部3が除去され
るに十分な厚さ丈は除去し、斯くて半導体基板本体1の
表面側に、熱質性層4の、その熱変性層4の表面側が少
くとも表面部6がi去されるに十分な厚さ丈は除去され
たことにより残された部(上述せる部2のろによる部)
による低抵抗半導体層5を得”、依って繊−V族化合物
半尋体基取本体1の表面側に低抵抗半導体層5を形成し
てなる構成の半導体基板6を得る(第1図C)。
Next, the semiconductor substrate body 1 is heat-treated to form a heat-denatured layer 4 on its surface side, and then the heat-denatured layer 4 is etched using, for example, a sulfuric acid-based aqueous solution to form a heat-denatured layer 4 on the surface side. is removed to a sufficient thickness that at least the surface portion 3 is removed, so that at least the surface portion of the thermally denatured layer 4 of the thermal layer 4 is removed on the surface side of the semiconductor substrate body 1. The part that is thick enough for 6 to be removed is the part that remains after being removed (the part due to the part 2 mentioned above)
Thus, a semiconductor substrate 6 having a structure in which a low-resistance semiconductor layer 5 is formed on the surface side of a fiber-V group compound semi-solid base body 1 is obtained (FIG. 1C). ).

次に斯く得られた半導体基板6を用いて半導体素子とし
てショットキ接合微電界効果トランジスタを形成すべく
、その半導体基&6の低抵6抗半尋体層5上に、所要の
パターンを有するソース電極7及びドレイン電極8を、
例えばAuGa  台金の真空蒸着処理、例えば水素ガ
ス中での例えば460℃、例えば5分の熱処理を含んで
、低抵抗半導体層5とオーミック接触せるものとして形
成しく第1図D)、次で低抵抗半導体層5上に、ソース
電極7及びドレイン電極8間の領域に於てゲート電極9
を、例えばMの真空蒸着処理を含んで、低抵抗半導体層
5との間でショットキ接合10を形成すべく形成しく第
1図E)、然る后、低抵抗半導体層5に対するメナエッ
チング処理により、低抵抗半導体層5の不要な領域を除
去し、斯くて半導体素子としてのショットキ接合型電界
効果トランジスタM1を形成してなる目的とせる半導体
装置を得る(第1図F)。
Next, in order to form a Schottky junction micro-field-effect transistor as a semiconductor element using the semiconductor substrate 6 thus obtained, a source electrode having a required pattern is formed on the low-resistance half-layer 5 of the semiconductor substrate &6. 7 and the drain electrode 8,
For example, the AuGa base metal is formed into ohmic contact with the low-resistance semiconductor layer 5 by vacuum evaporation treatment, for example, heat treatment in hydrogen gas at 460° C. for 5 minutes, etc. A gate electrode 9 is formed on the resistive semiconductor layer 5 in a region between the source electrode 7 and the drain electrode 8.
is formed to form a Schottky junction 10 with the low-resistance semiconductor layer 5, including, for example, a vacuum evaporation process of M (FIG. 1E), and then by a Mena etching process on the low-resistance semiconductor layer 5. Then, unnecessary regions of the low-resistance semiconductor layer 5 are removed, thereby obtaining the desired semiconductor device in which a Schottky junction field effect transistor M1 as a semiconductor element is formed (FIG. 1F).

以上にて本発明による半導体装置の一例構成(第1図F
)及びその製法の一例が明らかとなったが、本発明によ
る半導体装置の一例構成によれば、それが深い単位を形
成する不純物としてのOr  の添加により半絶縁性化
されてなるGIAs ’pなる門−■族化合物牛導体本
体1でなる半絶縁性半導体基板本体の表面側に、低抵抗
半導体層5でなる低抵抗半導体層を形成してなる構成の
半導体基板6でなる半導体基板を用いて、ショットキ接
合型電界効果トランジスタM1でなる半導体装置を形成
してなる構成を有し、そしてこの場合、半導体基板(半
導体基板6)が、半4e縁性半導体基板本体(深い準位
を形成する不純物としてのcr  の添加により半絶縁
化されてなるGaAs  でなる囲−■族化合物半導体
基板本体1)を用いた半導体基板であるので、従来の斯
種半導体装置の場合と同様に、半導体基板を用いて形成
された半導体素子(ショットキ接合型電界効果トランジ
スタM1 )を互に分離されてなるものとして構成する
ことが出来、又半導体素子を浮遊容量の小なるものとし
て構成することが出来るという特徴を有するものである
An example of the configuration of the semiconductor device according to the present invention (FIG. 1F) has been described above.
) and an example of its manufacturing method have been clarified, and according to an example configuration of a semiconductor device according to the present invention, it is made semi-insulating by adding Or as an impurity to form a deep unit. Using a semiconductor substrate consisting of a semiconductor substrate 6 having a configuration in which a low resistance semiconductor layer 5 is formed on the surface side of a semi-insulating semiconductor substrate body consisting of a conductor body 1 made of a group compound compound. , has a configuration in which a semiconductor device is formed of a Schottky junction field effect transistor M1, and in this case, the semiconductor substrate (semiconductor substrate 6) is a semi-4e edge semiconductor substrate body (impurity forming a deep level). Since this is a semiconductor substrate using a GaAs group compound semiconductor substrate body 1) which has been made semi-insulating by adding cr as The semiconductor element (Schottky junction field effect transistor M1) formed by the semiconductor device can be configured as being separated from each other, and the semiconductor element can be configured as having a small stray capacitance. It is something.

然し乍ら本発明による半導体装置の場合、その半導体基
板(半導体基板6)を構成せる牛絶縁性半導体基版本体
(深い準位を形成する不純物としてのOr  の添加に
より半絶縁化されてなるGaAs  でなる■−V族化
合物半導体基板本体1)が深い準位を形成する不純物(
Or)  の松加により半絶縁性化されてなるMl−V
族化合物半導体(GaAs )  でなり、そして低抵
抗半導体層(低抵抗半導体層5)が、深い準位を形成す
る不純物(Or)の添加番こより半絶縁化されてなる石
−■族化合物半導体(GaAa)  に対する熱処理に
より、その謙−■族化合物半導体の表面側に形成された
熱変性層(熱変性層4)の、その熱変性層の表面側が所
要の厚さ丈は除去されたことにより残された部でなるの
で、その低抵抗半導体層(低抵抗半導体層5)が格段的
に大なる電子移動度を有するものである。因みに、本発
明による上剥の場合、電子移動度が室温で6500cI
i/V−1・Cの値を有し、低抵抗半導体層が従来みら
れる如くにイオン打込法によって形成されているものと
した場合の約1.2倍の値を有するものである。又この
為半導体素子(ショットキ接合型電界効果トランジスタ
M1)が高性能を南するものである。因みに、本発明に
よる上剥の場合、相互コンダクタンスが、低抵抗半導体
層が従来みられる如くにイオン打込法によって形成され
ているものとした場合の約2倍、エピタキシャル成長法
によって形成されているものとした場合の約12倍の値
を有するものである。
However, in the case of the semiconductor device according to the present invention, the semiconductor substrate (semiconductor substrate 6) is composed of an insulating semiconductor substrate body (made of GaAs made semi-insulating by adding Or as an impurity to form a deep level). ■-V group compound semiconductor substrate body 1) contains impurities (
Ml-V made semi-insulating by Matsuka of Or)
A GaAs group compound semiconductor (GaAs), in which a low resistance semiconductor layer (low resistance semiconductor layer 5) is made semi-insulating by adding an impurity (Or) to form a deep level. Due to the heat treatment of GaAa), the heat-denatured layer (thermal-denatured layer 4) formed on the surface side of the humble-III group compound semiconductor is removed to a required thickness, so that the remaining heat-denatured layer is removed. Therefore, the low resistance semiconductor layer (low resistance semiconductor layer 5) has a significantly high electron mobility. Incidentally, in the case of the top layer according to the present invention, the electron mobility is 6500 cI at room temperature.
It has a value of i/V-1.C, which is approximately 1.2 times the value when the low-resistance semiconductor layer is formed by conventional ion implantation. Also, for this reason, the semiconductor element (Schottky junction field effect transistor M1) has a high performance. Incidentally, in the case of the overlayer according to the present invention, the mutual conductance is approximately twice as high as that when the low-resistance semiconductor layer is formed by the epitaxial growth method as compared to the case where the low-resistance semiconductor layer is formed by the conventional ion implantation method. This value is about 12 times that of the case where

又上述せる本発明による半導体装置の製法の一例によれ
ば、それが深い準位を形成する不純物のみ加により半絶
縁化されてなる■−■族化合物半導体基板本体1を用意
しくw、1図A)、その石−V&化合物半導体基板本体
1に対する熱処理により当m1ll−V族化合物半導体
基板本体1の表面側に熱変性層4を形成しく第1図B)
、その熱変性層4の表面側を所要の厚さ丈は除去し、こ
れより■−V族化合物半尋体基板本体1の表面−に、熱
農性層4の、その熱変性層4の表向側が所要の岸さ丈は
除去されたことにより残された部による低抵抗牛導体i
@5を得、よって■−■族化合物半導体基板本体1の表
面側に低抵抗半導体1−5を形成してなる構成の半導体
基板6を得(第1図C)、その半導体基板6を用いてF
9T要の半導体素子(ショットキ接合m11L界効釆ト
ランジスタMl)を形成するという方法であるので、前
述せる^性能を有する半導体素子を、簡易容易に形成す
ることが出来°るという大なる特徴を有するものである
According to an example of the method for manufacturing a semiconductor device according to the present invention described above, a ■-■ group compound semiconductor substrate body 1 is prepared, which is made semi-insulating by adding only impurities that form a deep level. A), by heat treatment of the stone-V & compound semiconductor substrate body 1, a thermally denatured layer 4 is formed on the surface side of the m1ll-V group compound semiconductor substrate body 1 (FIG. 1B)
, remove the surface side of the heat-modified layer 4 to a required thickness, and then apply the heat-modified layer 4 of the thermo-agricultural layer 4 to the surface of the V group compound semi-solid substrate body 1. The required bank height on the front side is the low resistance conductor i due to the part left after being removed.
@5, thus obtaining a semiconductor substrate 6 having a structure in which a low resistance semiconductor 1-5 is formed on the surface side of the ■-■ group compound semiconductor substrate body 1 (FIG. 1C), and using this semiconductor substrate 6. TeF
Since this method forms a 9T semiconductor element (Schottky junction m11L field effect transistor Ml), it has the great feature that a semiconductor element having the above-mentioned performance can be formed simply and easily. It is something.

次に、本発明による半導体装置の他の例及びその製法の
一例を、第2図を伴なってその製法の一例を以って述べ
るに、深い準位を形成する不純物Fe  の添加により
半絶縁性化されてなるInPでなる■−■族化合物半導
体基板本体21を予め用意する(第2図A)。
Next, another example of the semiconductor device according to the present invention and an example of its manufacturing method will be described with reference to FIG. 2. A ■-■ group compound semiconductor substrate body 21 made of chemically modified InP is prepared in advance (FIG. 2A).

而してそのm−■族化合物半導体基板本体21に対する
、例えば800℃、例えば7時間の熱処理を、例えば1
気圧のP蒸気圧を有する雰囲気にてなす。然るときは、
半導体基板本体21の表面側に於て、それに添加されて
いる不純物としてのF・が半導体基板本体21の表面に
向って拡散乃至輸送し、この為第2図Bに示す如く半導
体基板本体21の表面側に、不純物としてのF・ を殆
んど含有していないか含有しているとしても熱処理前に
比し格段的に少ない菫しか含有していない、従って低抵
抗を呈している部22と、その部22上のF・ を熱処
理前に比し多重に含有している表面@25とを有する熱
変性層24が形成されるものである。尚この場合熱変性
層24は、これを部22をしてa4μm1表面部23を
して11μmの厚さを有するものとして形成し得るもの
である。
Then, the m-■ group compound semiconductor substrate body 21 is heat-treated at, for example, 800° C. for, for example, 7 hours, for example, for 1 hour.
This is done in an atmosphere having a P vapor pressure of atmospheric pressure. When it happens,
On the surface side of the semiconductor substrate body 21, F. as an impurity added thereto is diffused or transported toward the surface of the semiconductor substrate body 21, and as a result, as shown in FIG. On the surface side, there is a portion 22 that contains almost no F as an impurity, or even if it does, contains significantly less violet than before heat treatment, and therefore exhibits low resistance. , a heat-denatured layer 24 having a surface @25 containing more F. on the portion 22 than before the heat treatment is formed. In this case, the thermally denatured layer 24 can be formed to have a thickness of 11 μm, with the portion 22 having a thickness of 4 μm and the surface portion 23 having a thickness of 11 μm.

次に、斯く半導体基板本体21°に対する熱処理により
、その表面側に熱変性層24を形成して后、その熱変性
層24#c対する例えば臭素−メタノール溶液を用いた
エツチング処理により、熱変性層24の表面側を少くと
も表面部23が除去されるに十分な厚さ丈は除去し、斯
くて半導体基板本体21の表面側に、熱変性層24の、
その熱変性層24の表面側が少くとも表面部26が除去
されるに十分な厚さ丈は除去されたことにより残された
部(上述せる部22のみによる部)による低抵抗半導体
層25を得、依って■−■族化会物半導半導°板本体2
1の表向側に低抵抗半導体層25を形成してなる構成の
半導体基板26を得る(第2図0)。
Next, the semiconductor substrate body 21° is heat-treated to form a heat-denatured layer 24 on its surface side, and then the heat-denatured layer 24#c is etched using, for example, a bromine-methanol solution. 24 is removed to a sufficient thickness that at least the surface portion 23 is removed, and thus the heat-denatured layer 24 is removed on the surface side of the semiconductor substrate body 21.
The surface side of the heat-denatured layer 24 has a thickness sufficient to remove at least the surface portion 26, and a low-resistance semiconductor layer 25 is obtained by the remaining portion (the portion formed only by the above-mentioned portion 22). Therefore, ■-■ group compound semiconductor semiconductor board main body 2
A semiconductor substrate 26 having a structure in which a low resistance semiconductor layer 25 is formed on the front side of the semiconductor substrate 1 is obtained (FIG. 20).

次に斯く得られた半導体基板26を用いて半導体素子と
して蓄積型(MIa型)電界効果トランジスタを形成す
べく、その半導体基板26の低抵抗半導体層25上に、
所要のパターンを有するソース電極27及びドレイン電
極28を1例えばjku8n  合金の真空蒸着処理、
例えば水素ガス中での例えば400℃、例えば3分の熱
処理を含んで、低抵抗半導体層25とオーミクク誉触せ
るものとして形成しく第2図D)、次で低抵抗半導体層
25及び半導体基板26に対する例えば臭素−メタノー
ル溶液を用いたメサエッチング処理により、ソース電極
27及びドレイン電極28間の領域に於て、低抵抗半導
体層25の全厚味を通じて半導体基板26内に達する#
I51を形成すると共に、低抵抗半導体層25の不要な
領域を除去しく第2図113)、次で溝51の内面及び
、これに続く低抵抗半導体層25の表面上に延長せる絶
縁層50を、例えば陽極酸化法を含んで形成しく第2図
F)、次で絶縁層30に、溝51上のfj城に延長せる
ゲート電極29を、例えば111 の真空蒸着処理を含
んで形成し、斯くて半導体素子としての蓄積型(MIS
型)電界効果トランジスタM2を形成してなる目的とせ
る半導体装置を得る(第2図G)。
Next, in order to form an accumulation type (MIa type) field effect transistor as a semiconductor element using the semiconductor substrate 26 obtained in this way, on the low resistance semiconductor layer 25 of the semiconductor substrate 26,
A source electrode 27 and a drain electrode 28 having a desired pattern are formed by vacuum evaporation treatment of, for example, a jku8n alloy.
For example, the low-resistance semiconductor layer 25 and the semiconductor substrate 26 are formed into ohmic contact with the low-resistance semiconductor layer 25 by heat treatment at 400° C. for 3 minutes in hydrogen gas, for example. For example, by mesa etching using a bromine-methanol solution, # reaches into the semiconductor substrate 26 through the entire thickness of the low resistance semiconductor layer 25 in the region between the source electrode 27 and the drain electrode 28.
At the same time as forming I51, an unnecessary region of the low resistance semiconductor layer 25 is removed (FIG. 2 113), and then an insulating layer 50 is formed to extend over the inner surface of the groove 51 and the subsequent surface of the low resistance semiconductor layer 25. Then, a gate electrode 29 is formed on the insulating layer 30 by using, for example, a vacuum evaporation process of 111, which can be extended to fj on the groove 51 (FIG. 2F). storage type (MIS) as a semiconductor device.
A desired semiconductor device is obtained by forming a field effect transistor (type) M2 (FIG. 2G).

以上にて本発明による半導体装置の他の例の構成(第2
図G)及びその製法の一例が明らかとなったが、その本
発明による半導体装置の構成によれは、それが深い準位
を形成する不純物としてのF、  の姫加により半絶縁
性化されてなるInPでなる石−■族化合物半導体基板
本体21でなる半絶縁性半導体基板本体の表向側に、低
抵抗半導体層25でなる低抵抗半導体層を形成してなる
構成の半導体基板26でなる半導体基板を用いて、低抵
抗半導体層25の1s51にて分離されてなる領域32
及び33を夫々ソース領域及びドレイン領域とせる蓄積
型(MIS型)m界効果トランジスタM2でなる半導体
装置を形成してなる構成を有し、そしてこの場合、半導
体基板(半導体基板26)か、半絶縁性半導体基板本体
(深い単位を形成する不純物としてのFe  の咋加に
より半絶縁化されてなるlnPでなる崩−■族化合物半
導体基板本体2°1)を用いた半導体基板であるので、
従来の斯種半導体装置の場合と同様に、半導体基板を用
いて形成された半導体素子(蓄積型(MI S型)11
界効果トランジスタM2)を互に分離されてなるものと
して構成することが出来、又半導体素子を浮遊容量の小
なるものとして構成することが出来るという特徴を有す
るものである。
The structure of another example of the semiconductor device according to the present invention (second example) has been described above.
Figure G) and an example of its manufacturing method have been revealed, but the structure of the semiconductor device according to the present invention makes it semi-insulating due to F as an impurity that forms a deep level. A semiconductor substrate 26 has a structure in which a low resistance semiconductor layer 25 is formed on the front side of a semi-insulating semiconductor substrate body 21 made of InP. Regions 32 separated by 1s51 of the low resistance semiconductor layer 25 using a semiconductor substrate
and 33 as a source region and a drain region, respectively, to form a semiconductor device consisting of an accumulation type (MIS type) m-field effect transistor M2, and in this case, the semiconductor substrate (semiconductor substrate 26) or the Since it is a semiconductor substrate using an insulating semiconductor substrate body (a 2°1 insulating semiconductor substrate body made of lnP which is semi-insulated by the addition of Fe as an impurity forming a deep unit),
As in the case of conventional semiconductor devices of this kind, a semiconductor element (storage type (MIS type) 11 formed using a semiconductor substrate)
This device has the characteristics that the field effect transistors M2) can be constructed as being separated from each other, and that the semiconductor element can be constructed as having a small stray capacitance.

然し乍ら本発明による半導体装置の場合、その半導体基
板(半導体基板26)を構成せる半絶縁性半導体基板本
体(深い準位を形成する不純物としてのF・ の添加に
より半絶縁化されてなるInPでなるl−■族化合物牛
導体基板本体2旬が深い準位を形成する不純物(Fe)
  の添加番こより半絶縁性化されてなる■−■族化合
物半導体(InP)でなり、そして低抵抗半導体層(低
抵抗半導体層25)が、深い準位を形成する不純−(F
・)の添加により半絶縁化されてなる川−V族化合物半
導体(Ink)に対する熱処理ζこより、その門−v族
化合物半導体の表面側に形成された熱変性層(熱変性層
24)の、その熱変性層の表面側が所要の厚さ丈は除去
されたことにより残された部でなるので、その低抵抗半
導体層(低抵抗半導体層25)を所要の大なる厚さを有
し且縮装の比抵抗を有するものとして形成することか出
来るものである。この為半導体素子(蓄積型(MlS型
)電界効果トランジスタM2)を鵜性能を有するものと
して形成することが出来るものである。因みに、本発明
による上剥の場合、相互コンダクタンスを、70m5/
mm O)値で得ることが出来、低抵抗半導体層が従来
みられる如くにエピタキシャル成長法によって形成され
ているものとした場合に比し格段的に大なる値を有する
ものとして得られるものである。
However, in the case of the semiconductor device according to the present invention, the semiconductor substrate (semiconductor substrate 26) is composed of a semi-insulating semiconductor substrate body (made of InP made semi-insulating by adding F as an impurity to form a deep level). Impurity (Fe) that forms a deep level in the second layer of the l-■ group compound conductor substrate body
The low-resistance semiconductor layer (low-resistance semiconductor layer 25) is made of a ■-■ group compound semiconductor (InP) that is semi-insulating due to the addition number of .
The heat treatment ζ of the Kawa-V group compound semiconductor (Ink) made semi-insulating by the addition of . Since the surface side of the heat-denatured layer is the part left after the required thickness is removed, the low-resistance semiconductor layer (low-resistance semiconductor layer 25) has the required large thickness and shrinkage. It can be formed as having a specific resistance of 100%. Therefore, it is possible to form a semiconductor element (storage type (MlS type) field effect transistor M2) as having a corroboration performance. Incidentally, in the case of the top stripping according to the present invention, the mutual conductance is 70m5/
mm 2 O) value, which is much larger than that in the case where the low resistance semiconductor layer is formed by the epitaxial growth method as seen in the past.

又第′2図にて上述せる本発明による半導体装置の製法
の実施例によれば、それが深い準位を形成する不純物の
添加により半絶縁化されてなる■−v族化合物半導体基
板本体21を用意しく第2図人)、そのi+t −V族
化合物半導体基板本体21に対する熱処理により当該辺
−■族化合物牛導体基板本体21の表面側に熱変性層2
4を形成しく第2図B)、その熱変性層24の表向側を
所要の厚さ丈は除去し、これよりl−■族化合物半導体
基板本体21の表面側に、熱変性層24の、その熱変性
層24の表向側か所要の厚さ丈は除去されたことにより
残された部による低抵抗半導体層25を得、よってm−
■族化合物半導体基板本体21の表面側に低抵7抗半導
体層25を形成してなる構成の半導体基板26を得(第
2WAO)、その半導体基板26を用いて所要の半導体
素子(11横型(MIS型)電界効果トランジスタM2
)を形成するという方法であるので、前述せる高性能を
有する半導体素子を、簡易容易に形成することが出来る
という大なる特徴を有するものである。
Further, according to the embodiment of the method for manufacturing a semiconductor device according to the present invention described above in FIG. (see Figure 2), heat treatment is performed on the i+t-V group compound semiconductor substrate body 21 to form a heat-denatured layer 2 on the surface side of the side-I group compound semiconductor substrate body 21.
4 (FIG. 2B), remove the required thickness from the front side of the heat denatured layer 24, and then form the heat denatured layer 24 on the front side of the l-■ group compound semiconductor substrate body 21. , the required thickness from the front side of the heat-denatured layer 24 is removed to obtain a low-resistance semiconductor layer 25 by the remaining portion, and thus m-
A semiconductor substrate 26 having a structure in which a low-resistance semiconductor layer 25 is formed on the front surface side of a group (2) compound semiconductor substrate body 21 is obtained (second WAO), and the semiconductor substrate 26 is used to form a required semiconductor element (11 horizontal type). MIS type) field effect transistor M2
), it has the great feature that the semiconductor element having the above-mentioned high performance can be formed simply and easily.

尚上述に於ては牛絶縁性牛導体基板本体が、深い単位を
形成する不純物としてのCr又はFeの添加により半絶
縁性化されてなる■−V族化酋物半導体でなる場合につ
き述べたが、深い準位を形成する不純物としての酸素(
0)の添加により半絶縁性化されてなる■−■族化合物
半導体であっても、又そのm−V族化合物半導体がGa
As  又は1nP以外のものであっても、更には半導
体素子かショットキ接合型又は蓄積型(MIS型)’m
界効果トランジスタ以外のバイポーラ型トランジスタ、
ダイオード等であっても本発明を適用し得ること明らか
であろう。
In the above description, the main body of the insulating conductor substrate is made of a ■-V group compound semiconductor made semi-insulating by adding Cr or Fe as an impurity to form deep units. However, oxygen (
Even if the ■-■ group compound semiconductor is made semi-insulating by the addition of 0), the m-V group compound semiconductor may be Ga
Even if it is other than As or 1nP, it can also be used as a semiconductor device, Schottky junction type or accumulation type (MIS type).
Bipolar transistors other than field effect transistors,
It will be obvious that the present invention can be applied to diodes and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A−Fは本発明による半導体装置の一例及びその
製法の一例を示す、その製法の一例に於ける順次の工程
に於ける路線的断面1、第2図A−Gは本発明による半
導体装置の他の例及びその製法の一例を示す、その製法
の一例に於ける順次の工程に於ける路線的断面図である
。 図中1及び21は半絶縁化されてなる出−■族化合物中
導体基板本体、4及び24は熱変性層、5及び25は低
抵抗半導体層、6及び26は半導体基板、Mlはショッ
トキ接合型電界効果トランジスタ、M2は蓄積型(MI
S型)I11界効果トランジスタを夫々示す。 出願人 日本電信電話公社
1A to 1F show an example of a semiconductor device according to the present invention and an example of its manufacturing method. FIGS. FIGS. 3A and 3B are cross-sectional views illustrating sequential steps in an example of the manufacturing method, showing another example of a semiconductor device and an example of its manufacturing method. In the figure, 1 and 21 are semiconductor substrate bodies made of semi-insulated group III compounds, 4 and 24 are heat-denatured layers, 5 and 25 are low-resistance semiconductor layers, 6 and 26 are semiconductor substrates, and Ml is a Schottky junction. type field effect transistor, M2 is an accumulation type (MI
S type) I11 field effect transistors are shown respectively. Applicant Nippon Telegraph and Telephone Corporation

Claims (1)

【特許請求の範囲】 1、 半絶縁性半導体基板本体の表面側に低抵抗半導体
層を形成してなる構成の半導体基板を用いて所要の半導
体素子を形成してなる半導体装置に於て、上記半絶縁性
半導体基板本体が深い準位を形成する不純物の添加によ
り半絶縁性化されてなる■−■族化合物牛尋体でなり、
上記低抵抗半導体層が、上紀門−V族化合物半導体本体
に対する熱処理により当該l−■族化会物半導体本体の
表面側に形成された熱変性層の、当該熱変性層の表面側
が所要の厚さ丈は除去されたことにより残された部でな
る事を特徴とする半導体装置。 2、森い準位を形成する不純物の添加により半絶縁性化
されてなる謙−v族化合物半導体基板本体を用意し、該
■−■族化合物半導体基板本体に対する熱処理により当
該■−■族化曾物半導体基板本体の表面側に熱変性層を
形成し、該熱変性層の表面側を所要の厚°さ丈は除去し
、これにより上記嵐−■族化合物半導体本体の表面側に
、上記熱変性層の、当該熱変性層の表面側が所要の厚さ
丈は除去されたことにより残された部による低抵抗半導
体層を得、よって上記l−V族化合物半導体基板本体の
表面側に上記低抵抗半導体層を形成してなる構成の半導
体基板を得、該半導体基板を用いて所要の半導体素子を
形成する事を特徴とす□る半導体装置の製法。
[Claims] 1. In a semiconductor device in which a required semiconductor element is formed using a semiconductor substrate having a structure in which a low resistance semiconductor layer is formed on the surface side of a semi-insulating semiconductor substrate body, the above-mentioned The semi-insulating semiconductor substrate is made semi-insulating by adding impurities that form a deep level, and is made of a ■-■ group compound.
The low-resistance semiconductor layer is formed on the surface side of the I-III group compound semiconductor body by heat treatment of the Jokimon-V group compound semiconductor body. A semiconductor device characterized in that the thickness is determined by a portion left after being removed. 2. Prepare a semi-insulating semiconductor substrate made of a semi-insulating compound semiconductor substrate made of a semi-insulating material by adding impurities that form the Mori level, and heat-treat the compound semiconductor substrate to make it semi-insulating. A heat-denatured layer is formed on the surface side of the Arashi semiconductor substrate body, and the heat-density layer is removed to a required thickness and length, thereby forming the heat-density layer on the surface side of the Arashi-III group compound semiconductor body. The surface side of the heat-denatured layer is removed to a required thickness to obtain a low-resistance semiconductor layer by the remaining portion, and the above-mentioned layer is formed on the surface side of the l-V group compound semiconductor substrate body. A method for manufacturing a semiconductor device according to □, characterized in that a semiconductor substrate having a structure formed by forming a low resistance semiconductor layer is obtained, and a required semiconductor element is formed using the semiconductor substrate.
JP56180479A 1981-11-11 1981-11-11 Semiconductor device and manufacture thereof Granted JPS5882575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56180479A JPS5882575A (en) 1981-11-11 1981-11-11 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56180479A JPS5882575A (en) 1981-11-11 1981-11-11 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS5882575A true JPS5882575A (en) 1983-05-18
JPS6233741B2 JPS6233741B2 (en) 1987-07-22

Family

ID=16083935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56180479A Granted JPS5882575A (en) 1981-11-11 1981-11-11 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5882575A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994815A (en) * 1982-11-22 1984-05-31 Fujitsu Ltd Production of semiconductor device
JP2004273888A (en) * 2003-03-11 2004-09-30 Hitachi Cable Ltd Epitaxial wafer for field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994815A (en) * 1982-11-22 1984-05-31 Fujitsu Ltd Production of semiconductor device
JP2004273888A (en) * 2003-03-11 2004-09-30 Hitachi Cable Ltd Epitaxial wafer for field effect transistor

Also Published As

Publication number Publication date
JPS6233741B2 (en) 1987-07-22

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