JPS5883894A - Digital musical tone modulation device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital musical tone modulation device that temporally modulates a musical tone signal, and in which the musical tone signal is expanded and contracted digitally and temporally while keeping the sampling clock frequency constant. It is something.

Traditionally, musical tones have been modulated using amplitude modulation and insulating modulation.

There are many methods, such as delay modulation. One of the most widely used devices is the bucket pregate device (BB
As shown in D), the delay time is modulated by increasing or decreasing the transfer lock frequency of the charge transfer element using a modulation signal.

However, since the BBD is an analog device, it has the drawback of having a lot of residual noise. On the other hand, if a digital shift register is used, the noise is reduced, but since the frequency of the shift clock varies, there is a drawback that compatibility with peripheral systems, which originally have a constant clock frequency, is poor.

The present invention solves these conventional problems and provides a digital tone modulation device that can digitally apply delay modulation while keeping the sampling clock frequency constant.

First, the basic principle of the present invention will be explained. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, reference numeral 1 denotes a modulation signal generator which generates a modulation signal of a frequency lower than the audible band in the form of a digital code. Reference numeral 3 denotes a read/write memory having a plurality of addresses, which can sequentially store musical tone signals input from the input terminal 6 at predetermined addresses, and read out musical tone signals written and received at predetermined addresses. 2 is an address calculation circuit,
Using the self-generated address and the modulation signal, it generates a write address and a read address, and also generates interpolated data for compensation calculations. Reference numeral 4 denotes an interpolation calculation circuit which performs interpolation calculation on the musical tone signal output from the read/write memory 3 based on the interpolation data, and outputs the output signal from the output terminal 6.

The basic operation of FIG. 1 will be explained with reference to FIG. 2. Input terminal 6
Musical tone signal samples s,,s,Y11Si+21...W Si+81...
- When input, these are sequentially written to the read/write memory 3. The written sample is shown in Figure 2 (b
), the data is read after a certain time delay. The read sample is ``j41''I Sj+8. ””
.... If the data is output as is, there will only be a certain time delay. In the present invention, when reading a musical tone signal sample, two or more samples of S and 85+1 are read out, and interpolation is performed between them according to the magnitude of the modulation signal, and the result is shown in FIG. 2 (C). S.J.
Output. In this way, if the interpolated data fluctuates, the time at which the sample is output fluctuates, resulting in a fluctuation in delay time, that is, delay modulation. When reading (S,
, S, 1), if 1 is kept the same value and only the interpolation position changes, instead of increasing by 1, the time delay will increase significantly. On the other hand, if `` increases by 2 or more, the delay time becomes significantly smaller. As for how to increase j, the magnitude of the modulation signal may be added to the increment of 1 in writing to change the manner in which i increases.

Basically, the expansion and contraction of the long sword waveform on the time axis is performed based on the above-mentioned concept.

Since such an operation can be performed in synchronization with a fixed clock cycle, if this is performed in a time division multiplexed manner, it becomes possible to apply different modulations to a plurality of input signals.

Figure 3 explains the operating principle of time division multiplexing.
a) is the modulated signal M6. Mb, : Indicates that four types of Mc and Md are supplied in order. (b) is the input signal SSb,
It remains to be seen that S, , Sd are supplied in sequence. ((=) is gender, Mb, M,, Md (!: Sa, Sb, S,, Sd, and B, *, B b *, BC *,
This shows that Sd* can be obtained sequentially.

FIG. 4 is a block diagram of the first embodiment of the present invention.

1 is a modulation signal generator. 23 is write address l
A 7-bit counter that generates υ is counted down by the timing pulse φ. The 7-bit write address i is applied to gate 26 and its MSB
is inverted by the inverter 28 and becomes (i-N),
It is added to one input of the adder/subtractor 21. Adder/subtractor 21
A modulation signal is applied to the other input of. Adder/subtractor 21
The upper 7 bits of the output are the read address (1-N
+α) to the gate 27. Furthermore, this high-order bit is also added to the "1" adder 24, where it becomes "1".
is added to the second read address (j-N+a+1
) is added to the gate 26 as . Gate 26, 26
．． 27 have timing pulses φ, φ, φ, respectively.
is applied. Note that the timing pulse φ. , φ1.
φI2'' and φ3 are four-phase timing pulses as shown in FIG.

Then, the write address is written to the timing pulse φ1,
The first read address and the address are selected by the timing pulse φ2 and the second read exit address is selected by the timing pulse φ3 and applied to the address input AD of the read/write memory 31, respectively.

The read/write memory 31 is composed of a so-called random access memory consisting of 128 1-word 16-bit memories corresponding to 7-bit addresses. An input signal is applied from the input terminal 6 to the data input DI. When "1" is input to the write terminal WR, DI is written into the 16-bit memory cell designated by the address AD at the falling edge. When WR is roJ, one word of the address specified by address AD appears at output Do. 32 is a latch of 1 word and 16 bits, and the l clock is φ2, so the first read address (i-
N+a) samples are stored. 32 is also 1 word 16
Although it is a bit latch, since the clock is φ3, the sample of the second read address (i−N+α+1) is stored. These samples are denoted by s, , S,1(1,=t-N+α). Sample S1. S5+1 is added to a subtracter 41, and the difference (S-S) is calculated and added to a multiplier 42.

The lower bits of the adder/subtracter 21 are input to the other input of the multiplier 42 . The output of the multiplier 42 and the sample S1 are added to the adder/subtractor 43, and the sum thereof is outputted from the output terminal 6 as SI*.

Therefore, when the timing pulse φ is reached, the counter is set to 5, and when the timing pulse φ is reached, the sample Si is at the address i.
is written, and address (i-N
+α), read out Sj', tie Si+1, and calculate these SJ, ! :Sj for Sj+1
will then be output.

Next, the relationship between addresses and interpolation will be explained. Let T be the period of the timing pulse φ0.

The counter 23 is 1. A sample timing 5T is output corresponding to address i. The modulation signal is expressed by the following equation (1).

M(iT)=MTsincu, , iT - (1) One input of the adder/subtractor 21 is (i-N)T.

Therefore, the sum output TR (i T ) of the adder/subtractor 21 is z TH (lT)=(i-N)T+MM, Tsinnm
iT−・−・(2). ω is the angular frequency of modulation in rad/s.

MM represents the depth of modulation. Let it be N2MM. This means reading a position shifted by a maximum of M, T from the reading center position (f-N)T. M does not necessarily have to be an integer. It may also change over time. The second apex body in equation (2) is not necessarily an integer.

Here, divide TR(LT) by T and take the integer part,
It is. [ ] indicates rounding down to the decimal point.

α is an integer.

On the other hand, below the decimal point is (TH(iT) moduto T)/T ・----
−(4)).

Equation (3) means that if there is no modulation, the address AI that should originally be read out is (1-N), but due to the modulation signal, the address AI that is shifted by the second term α is read out. Equation (4) becomes (
It represents the difference between equations 2) and (3). That is, therefore,
Sample value Sjl at A5! :I am trying to find the sample value S in AI+ by linear interpolation.

The output of the multiplier 42 is obtained by multiplying the difference by a weight equal to the amount of interpolation data, and is Ta(iT) moduto T (S, j+1-8j)T . . . The output signal from the interpolation operation is s, *=, s, +(s, +1-sj)-E! L concave 7 jikuyu...(6).

Equation (3) corresponds to the upper 7 bits of the output of the adder/subtractor 21, and equation (4) corresponds to the lower bits. In FIG. 4, the modulation signal has a maximum of 17 bits, and the lower bits of the sum output of the adder/subtractor 21 are 10 bits. The upper seven bits of the modulated signal correspond to the integer part, the most significant bit of which becomes the sign bit. Since Q representing the amplitude is a 6-bit integer, the decimal part is the lower 10 bits. Therefore, since the deviation of the original center address -<= corresponds to 6 bits, +
It becomes 64. The read/write memory 31 has 128 addresses compared to 7-bit addresses, and the difference between the write address and the read center address is N-64, so what is ζ where the read address overtakes the write address? do not have. If the MM is kept small, this danger can be completely prevented.

The write address i and the read address As increase with the increase of 5, but in reality, they are represented by 7 pits, so it becomes a book with moduto of 2-128, and the addresses on the read/write memory 31 are circularly written. will be moved.

FIG. 6 shows an embodiment in which the embodiment of FIG. 4 is used in time division multiplexing. The difference from FIG. 4 is that the counter 28
and multiplexer 14. The counter 28 receives the clock φ. The carry signal becomes the clock input of the counter 23, which is a 3-bit binary counter that counts up. The 3-bit output of the counter 28 is added to the lower 3-bit address AD2 of the read/write memory 31. Eight types of one different input signal are sequentially input to the input terminal 6 .

Therefore, eight types of input signals are stored in the read/write memory 31 in order. Since the 3-bit output of the counter 28 is applied to the multiplexer 14, the eight types of modulation signals output from the modulation signal generator 1 are time-division multiplexed and applied to the adder/subtractor 21. If you do this, 8
one time slot TSO9TS1. TS2.・・・・・・
..., TS7 perform independent modulation on different input signals, and the results are obtained as output signals at the output terminal 6. The read/write memory 31 requires eight times the capacity, and each part operates at eight times the frequency φ.

~φ3.

Note that AD2 may be the upper 3 bits of the read/write memory. In this case, nothing essentially changes except the write and read arrays.

Next, the modulation image will be explained.

FIG. 6 is a block diagram showing a specific configuration of the modulation signal generator 1 and its peripheral circuits. Vibrato oscillator 11. Unsample oscillator 12. Each output of the Celeste oscillators 1 and 3 corresponds to the multiplexer 14 shown in FIG. The signals are multiplexed by the analog multiplexer 14', applied to the analog-to-digital converter 16, and sequentially converted into digital signals, which are added by 1 to the adder/subtractor 21 in FIG.

The counter 16 corresponds to the column 28 in FIG.

The vibrato oscillator 11 outputs an analog sine wave of approximately 6 Hz. The unsample oscillator 11 is a mixture of sine waves of approximately 6 Hz and approximately 1 Hz, and generates three types of sine waves whose phases differ by 12 oO. Celeste oscillator 13 is
Generates a four-phase sine wave or triangular wave of approximately o, esHz. In this way, all modulation signals conventionally used for modulation effects in analog systems can be utilized.

FIG. 7 shows a specific configuration of the modulation signal generator 1 and its peripheral circuits, which digitally generate a plurality of modulation signals. Reference numeral 110 denotes a read-only memory that digitally generates a vibrato waveform, and is sequentially read out by CK. 120 is a similar read-only memory for creating a three-phase unsampled modulation signal, and 130 is a similar read-only memory for creating other modulation signals. These outputs are multiplexed by a digital multiplexer 14''. 111...112, 113 are modulation envelope circuits that digitally create a ramp waveform for varying the degree of modulation, and control signal CK1U. /D1.CK2.
U/D2. Controlled by CKs and U/Ds. That is, when U/D becomes "1", the output increases from 0 to 1 digit according to CK, and when it reaches full scale, it maintains that value. When U/D becomes "0", it decreases by one digit and reaches zero. □ Fig. 8(a) shows the modulation envelope circuit 111. 121
'.

131 is shown in FIG. 8), which shows a timing chart of each part. In Fig. 8 (-), 200 is a D7 lip 7CI block, 201, 203, 267 are AND gates, 202 is an inverter, 204 and 206 are RS flip-flops, 206 is an OR gate, and 208 is an up/down circuit with a clear terminal CL. The counter 209 is a gate circuit that detects whether the outputs of the counter 208 are all 0 or all 1. With this configuration, as is clear from the timing chart in FIG. An output signal is obtained.Of course, by changing the CK cycle, the rising and falling speeds can be varied.

Returning to FIG. 7, each modulation envelope circuit 111.1
The outputs of 21 and 131 are also multiplexed by the multiplexer 17. The outputs of multiplexers 14 and 17 are multiplied together by multiplier 18, and the product is supplied to adder/subtractor 21 in FIG. - There are various other methods for using the modulation signal generator 1. For example, it may be possible to generate a sine wave as proposed by the inventors in patent application (46) dated October 16, 1986.

Note that the part including the interpolation calculation circuit 4 and the address calculation circuit 2
5. If you use a so-called pipeline configuration in which data is processed while latching it, the calculation speed can be increased.

Further, in the above description, linear interpolation using two samples has been described, but quadratic function interpolation can also be performed using three samples.

Furthermore, when the sampling period is sufficiently small, that is, when the number of samples is large, sufficiently accurate modulation can be performed by omitting interpolation data, omitting interpolation calculations, and changing only the readout position.

As explained above, in this development, a modulation signal generator, a read/write memory, and an address control device write to the read/write memory according to the write signal output from the address control device, and generate the modulation signal. The address m++ controller generates a read signal based on the output of the device, reads the input signal from the read/write memory, and obtains an output signal that modulates the input signal on the time axis. Therefore, there is no residual noise that occurs when analog elements such as BBD are used, and consistency with the stem is also improved by operating in synchronization with a clock cycle in the -1 range. Since it can be operated with a fixed cycle clock, it is easy to perform time division multiplexing, and it is also easy to apply vibrato, unsample, celeste, and other effects to the same signal or different signals with one device. can be done.

Furthermore, if an interpolation calculation device is added to perform interpolation calculations, sufficient modulation can be applied to musical tones even when the sampling period is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the present invention in detail; FIGS. 2(a), (b), and (Q) are for explaining the modulation principle of the present invention; FIG. 3(a), (b), (C)
4 is a block diagram of the first embodiment of the present invention. FIG. 6 is a block diagram of the second embodiment of the present invention. Figure 7 is a block diagram showing the modulation signal generator and its peripheral circuits used in Figures 4 and 6, and Figures 8 (-) and (b) are specific configurations of the modulation envelope circuit used in Figure 7. 2 is a block diagram and a time chart thereof. 1...Modulation signal generator, 2...Address calculation circuit, 3...Read/write memory, 4...
...Interpolation calculation circuit, name of agent: Patent attorney Nakao
Toshio and one other person Figure 1

Claims (1)

[Scope of Claims] (1) comprising a modulation signal generator, a read/write memory, and an address control device, the digitized input signal to be modulated is transmitted to the read/write memory according to a write signal output from the address control device; A read signal is generated by the address control device based on the output of the modulation signal generator, and the input signal is read from the read memory according to the read signal, and the input signal is read out from the read memory. A digital musical tone modulation device characterized in that an output signal modulated on an axis is obtained. @) Comprising a modulation signal generator, a margin writing memory, an address control device, and an interpolation calculation device, the digitized input signal to be modulated is transmitted to the read/write memory according to the write signal output from the address control device. and read out the input signal from the read/write memory by the address control device based on the output of the modulation signal generator, and modulate the input signal on the time axis by performing interpolation calculation in the interpolation calculation device. A digital musical tone modulation device characterized in that an output signal is obtained. (3) In the description of claim 2, a plurality of types of input signals are time-division multiplexed and input, and a read/write memo η
are provided corresponding to the plurality of types of input signals, the address control device sequentially receives the time-division multiplexed input signals to the read/write memory, and the interpolation calculation device receives the input signals read from the read/write memory. What is claimed is: 1. A digital musical tone modulation device characterized in that a time-division multiplexed output signal is obtained by time-division multiplexing multiplexed signals. (4) A digital musical tone modulation device according to claim 3, characterized in that a plurality of modulation signals are generated by time division multiplexing from a modulation signal generator. (6) A digital musical tone modulation device according to claim 3, characterized in that at least two of the time-division multiplexed input signals are the same signal. (6) In the statement of claim 2, the address control device is constituted by a write control control device and a read control device, and the write control device sequentially writes input signals to the read/write memory, and the read control device A digital musical tone characterized in that the input signal written a predetermined time later than the writing of the input signal 0 is read out, and the readout position is changed in accordance with a modulation signal output from a modulation signal generator. Modulator. (7) In claim 2, there is a reading/writing method. a random access memory having a predetermined address size; a write control device of the address control device writes the input signal cyclically to the random access memory; a read control device of the address control device; A digital musical tone modulation device characterized in that, based on the modulation signal, positions around a reading center position delayed by a predetermined position from the write position of the input signal are read out. (8) In the provisional claim 7, the readout control device is provided with an adder/subtracter for adding or subtracting a modulated signal at its readout center position, and the adder/subtracter outputs a sum or the sum thereof. A digital musical tone modulation device characterized in that the device is configured to output an upper part of the data as a readout position. (9) In the statement of claim 18, the upper part of the sum outputted by the adder/subtractor is set as the readout position, and multiple positions in the read/write memory including adjacent positions are read out, and multiple readout outputs are performed. and a lower part of the sum are input to an interpolation calculation device, and an output is obtained by interpolating the lower part of the sum by 1. (10) A digital musical tone modulation device according to claim 9, characterized in that the number of readout outputs is three, and interpolation is performed using a quadratic function. (11) A digital musical tone modulation device as set forth in claim 9, characterized in that the number of read outputs is two and linear interpolation is performed. (12. Claim 3 is characterized in that the time-division multiplexed output signals of the interpolation calculation device are converted into independent analog signals and used as musical tone signals. Digital musical tone modulation device. (13) In the description of claim 3, at least two or more of the time-division multiplexed output signals of the interpolation calculation device are added and converted into an analog signal. A digital musical tone modulation device characterized by: