JPS5893345A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the IC with multilayer structure by mounting wiring metals while being projected to the surfaces of the insulating films of a plurality of element pieces in which semiconductor elements are made to contain and stacking these element pieces. CONSTITUTION:The first and second element pieces are formed by silicon single crystal substrates 11, 12, a silicon single crystal film 2 in which an active element is shaped, the metal 4 for wiring, an insulating layer 5, an insulator layer 6 and a spinel layer 7. The first element piece and the second element piece are joined by the section of a broken line A-A', and a section between the metals 4 is connected with low-temperature solder. The substrate 11 is etched, metallic wiring is formed to the layer 7, and the metal 8 wired to the outside is set up. The third element piece is joined onto the structure in the section shown by a broken line B-B', and a section between metals 4 is connected with low-temperature solder.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device including a large number of semiconductor active elements.

A so-called semiconductor integrated circuit (semiconductor integrated circuit) in which a large number of semiconductor active elements are fabricated into individual semiconductor pieces and the necessary connections are made between them.
(hereinafter abbreviated as IC) are already widely used in the world. In order to meet this demand for ICE, conventional technology development has been to miniaturize the semiconductor active elements included in the ICE as well as the metal wiring used for mutual interconnection, increase the integration density, and further increase the size of the semiconductor element. Emphasis has been placed on increasing the degree of integration. In line with the direction of this technological development, in recent years, mold face processing technologies such as electron beam lithography technology, which allows for finer drawing than normal light exposure technology, have been developed, and a large number of basic ICs have been manufactured within the plane of silicon wafers. and connect them to each other, essentially creating an Ic
f) Face! Techniques to increase this are being considered.

However, regarding miniaturization, there is no need to simply use equipment that performs microfabrication.
In addition to other high costs, it has been found that there are various practical constraints such as malfunctions due to natural radioactivity, and furthermore, in increasing the size of ICs, there is a reduction in yield and other practical limitations. There are restrictions.

In order to solve these problems, studies have begun to consider the possibility of a structure (hereinafter abbreviated as 3DIC) in which active elements are stacked in multiple layers to increase the integration density, whereas the conventional structure basically includes only one layer of active elements. There is.

According to the basic idea of 3DIC, Hc is first created on a semiconductor wafer using conventional technology, then covered with an insulating layer, and then
A wiring terminal for signal transmission is created in a part of P3o, and then a friend such as polycrystalline silicon is deposited on top of it.
The polycrystal is turned into a single crystal film using an O heating means such as an annealing ring, and the second layer 10 ICs that meet the active elements are created using the single crystal film, and this process is repeated one after another. It has a multi-layered structure and is used to make 93 DICs.

However, such a method is not only technically difficult to implement, but also requires a long production time.
It contains many essential ms such as l# retention drop.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve these OJI problems.

According to the present invention, a piece 10 having a layered structure consisting of two or more layers and containing a plurality of semiconductor active elements in at least one layer of the layer is a piece 10 having a layer structure consisting of two or more layers, and a piece 10 having a layer structure including a plurality of semiconductor active elements. The active element contained in the 10th element/piece and the active element contained in the 20th element piece are superimposed on the second element so that they are very close to each other, and the At least two or more electrical connections are made between the first piece of wood and the second piece of wood, and then some layers of the layer structure of the M-th piece that do not contain a semiconductor active element are connected. jI
Next, add a third element having the same structure as the second element from the first and fourth rattan elements, and then add a third element having the same structure as the second element from the first and fourth pieces. At least two or more electrical connections are made between the 10th piece and the 30th rattan piece within the overlapping plane on the sides close to the surface containing the manufactured semiconductor active element. According to the present invention, there is provided a method for manufacturing a semiconductor device characterized in that the structure of the inner three pieces of the first semiconductor device manufacturing method is the same as that of the sixth piece. Do the same operation as 9 for the elemental piece, also for the third elemental piece, overlap the fourth elemental piece, and IK
A method for manufacturing a semiconductor device according to claim 8 (1) is obtained in which a large number of elemental pieces such as all 1, 5, 6 etc. are laminated.

The details of the present invention will be explained below using examples.

In order to realize this embodiment, there is a membership fee for preparing at least 31i pieces. The second of these.

The third elemental piece is an elemental piece obtained by conventional integrated one-way technology. The first element piece is made on a so-called insulating film and is a silicon single crystal (abbreviated as SO1), and in this example, aluminum and magnesium oxides are formed on a silicon substrate. Spinel is epitaxially grown using a vapor phase growth method, a silicon single crystal film is further grown on top of the spinel, and a memory is fabricated in the silicon single crystal film using conventional manufacturing techniques.゛Among each of these fragments 0M08)? A schematic cross-sectional view of the resistor and wiring portion is shown in FIG.

Part iwA (a) is a schematic cross-sectional diagram of the second and third fragments (
B) is a schematic diagram of the cross section of the first element. In figure 0, 1 is a silicon single crystal substrate, 4 and 22 are diffusion layers, 3 is a silicon single crystal film, 3 is a gate electrode, 41 and 2 are for wiring. 51. 52 and & are silicon dioxide films, 6 is an insulating film, 41 is silicon oxide separately added to make the surface flat, and 7 is a single crystal spinel layer. be.

The ninth part is soldered at low temperature.

As is clear from this figure, one of the characteristics of these pieces is that the wiring metal is collected from the surface of the insulating film 60, and in this example, the Hiro low temperature solder core is The height is 2000 angstroms and the center is exposed.

Examples of the present invention are carried out by combining these pieces, and the procedure will be described below.

First, place the first piece on top of the second piece so that the low-temperature solder overlaps, apply a pressure of about 1000 grams per square meter, heat it to 400°C, and apply low-temperature solder. Connect C.

The o*mo* equation diagram of the state connected in this way is shown in (a) of FIG. In this figure, the cross-sectional line of the element is simplified, but the upper part of the broken line AI in the figure is the first element.
The lower part is a piece of iris. In the figure, 11 and 12 are silicon single crystal substrates, 2 is a silicon single crystal film on which active elements in the first element are made, 5 is an insulating layer, and 4 is a metal for wiring. The metal wiring 40 is connected with low temperature solder.

9. 6 in the figure is a single layer of insulation, but generally there is a space between the two holes, but if the protrusion of the low-temperature solder 00 in Figure 1 is made much smaller (reducing it to about 2000 ongest low 5 or less) Substantially, the insulation layer 61Wl is completely Kl! Arrive F. In order to further improve this adhesion, an insulating layer 60 is added.
An adhesive substance may be applied to the 11 surfaces. 7 is a spinel layer in this example.

Next, in the structure shown in FIG. 2(a), the silicon single crystal substrate 11 is etched using ordinary chemical etching (in this example, a mixture of nitric acid and fluoro-hydrochloric acid), and the 11 sides of the spinel layer 7 are etched using ordinary chemical etching. A pattern is formed using the method described above, and a portion of the spinel layer is removed to form metal wiring. A schematic cross-sectional view of state O at this stage is shown in 2nd H). 2.4 in the figure. a
, 7, 12.5 are the same as in Diagram 2 (a)) 8 is a metal for passing through the spinel 7 and wiring to the outside], 80
To number with low temperature solder similar to the 82nd company No. 1E kudzu on the surface.

Next, the three pieces of KJI are stacked on top of each other and heated and pressurized in the same manner as described above in the same manner as described above, to complete the feathers of Patent Claim OSS No. 1 as shown in No. 2 (c).

In the figure, 12, 21, 4. s, 17.8 is this figure (
A) and (B) are the same, and from the broken line B B', the third elemental piece of the first company is ToII), and the space between the rattan three elemental piece and the first elemental piece is also the same as the turtle- and 1s2 elemental pieces. It was possible to eliminate the space between the pieces in the same way as the method of substantially eliminating the space between the pieces. When used as a piece of wood, a fourth piece of wood, a fifth piece of wood,
..., it is possible to realize a semiconductor device having three or more layers containing active elements, and the invention of the patent application fIN, lI happiness item 2 is completed. O Although the present invention has been described above with reference to one embodiment, the present invention has solved the conventionally difficult problems of the 293 DICO 1 m manufacturing method.

In addition, in this example, single crystal spinel was used as the material for the first element, and 980I was used, but the 5oxo manufacturing method was not limited to this, and if the final 8016 structure was obtained, laser annealing, Many variations are possible, such as introducing oxygen into silicon to form a silicon dioxide layer and epitaxially growing silicon on top of the silicon dioxide layer. The final Ka wafer is large! Some perverts are possible, even if it's good! It is obvious that a 4hO semiconductor such as gallium arsenide may be used instead of silicon as the material used for K.

[Brief explanation of drawings]

JIIIg is M in the elemental piece O constituting the present invention O-Example
FIG. 2 is a schematic cross-sectional view of an OS) transistor and a wiring section. , FIG. 2 is a schematic cross-sectional view of the main steps in laminating the element pieces according to the method of the present invention. The number lines in the figure indicate the following. In jlllml, l...Silicon single crystal substrate, 4n...Diffusion layer, Phantom...Silicon single crystal film, 3...Gate electrode, 41,4! ...
...Wiring metal, 51,52.53...Silicon dioxide film, 6...Insulating film, ?・・・・・・
Single crystal spinel layer, C...low temperature solder. In the M2 diagram, 11, 12... silicon single crystal substrate, 2... silicon single crystal film, 4...
... Wiring metal 5 ... Insulating layer, 6 ...
- Insulating layer, 7... Spinel layer 8... Wiring metal, &... Low temperature solder. In addition, in FIG. 2 (a) KsP, the broken line hN is the boundary between the first piece of wood and the second piece of wood, and in (c) the broken line B B/
is the boundary between the first and third fragments. Diagram I (b) Hem Z diagram -

Claims (1)

[Claims] 1. A first device having a layered structure consisting of two or more layers, in which at least one of the layers includes a plurality of semiconductor active elements.
A piece of wood is placed on a second piece containing a plurality of semiconductor active elements so that the active elements included in the first piece and the active elements included in the second piece are close to each other. ,
At least two or more electrical connections are made between the first element piece and the second element piece within the overlapping plane, and then a semiconductor active element in the layer structure of the first element piece is formed. First, a third element having the same structure as the first element or the second element is removed so that the surface including the semiconductor active element is the jIl and the third element. 2 pieces made from the first piece and stacked on the side close to the surface containing the semiconductor active element, and at least two pieces are placed between the first piece and the Soki iris piece in the axillary overlapping plane. A method of manufacturing a semiconductor device characterized by performing the above electrical connection. In a method for manufacturing a semiconductor device, the structure of the third elemental piece is the same as the first piece of wood, the same operation performed on the first piece of wood is performed on the third elemental piece, and then the fourth elemental piece is Overlap the pieces,
The method for manufacturing a semiconductor device according to claim jI1, further comprising sequentially stacking a large number of pieces, such as fifth and sixth pieces.