JPS58182247A - Formation of projected electrodes of semiconductor device - Google Patents
Formation of projected electrodes of semiconductor deviceInfo
- Publication number
- JPS58182247A JPS58182247A JP57064802A JP6480282A JPS58182247A JP S58182247 A JPS58182247 A JP S58182247A JP 57064802 A JP57064802 A JP 57064802A JP 6480282 A JP6480282 A JP 6480282A JP S58182247 A JPS58182247 A JP S58182247A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- solder
- electrode
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
Landscapes
- Electronic Switches (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体基板にメッキ等で突起電極を形成する
場合の共通電極の除去方法に関する〇従来に半導体装置
等に突起電極を形成する場合全面に共通電極層を形成し
、レジストヲ用いて必要部にメッキ等で突起電極を形成
し、その後レジスト及び共通電極ン除去していた。該共
通電極層が複数の場合順次上層から下層へとエツチング
等で除去していたりこの様な場合、半導体装置に形成さ
れているパッシベーション膜、その下に形成されている
配線層、及び突起電極の形状に大きな制約がありこのた
めデバイスの微細パターン化が進んでもポンディングパ
ッド等の突起電極形成部のマイクロピッチ化が困難であ
った。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for removing a common electrode when a protruding electrode is formed on a semiconductor substrate by plating, etc. Conventionally, when a protruding electrode is formed on a semiconductor device, etc., a common electrode layer is formed on the entire surface. However, using a resist, protruding electrodes were formed in the necessary areas by plating or the like, and then the resist and common electrode were removed. If there are multiple common electrode layers, they are removed by etching or the like from the upper layer to the lower layer. There are major restrictions on the shape, and even if devices become more and more finely patterned, it has been difficult to achieve micropitch formation of protruding electrodes such as bonding pads.
本発明はかかる点に着目し、その目的とするところは、
上記欠点を解消しマイクロピッチ化可能な突起電極形成
法を提供する事にある・次に、半導体装置に半田突起電
極を形成する場合を例に図面にて説明する・
第1図、第2図、第3図は従来例を示す要部断面図で1
はシリコン基板、2はシリコン基板1上にAl 配線
で形成されたボンディング電極、3はパッシベーション
膜でボンディング電極2上の一部が開口している。4が
Cr、C,L等の金属より成る共通電極層でシリコン基
板1に全面蒸着等で形成される。07t はパッシベー
ションM3、ポンデインク電極2への密着力確保のため
、及びCtL層とポンディング電極2であるAt膜との
拡散ノ(リアの役目を持っており、CV 膜は突起電極
形成に向いている事から用いられている。5はメツキレ
シスト、6突起電極の下地で数μmメッキされたCu
層、7は前記CtL 層6上に数10μmメッキされた
Pb−8nハ/ダである。このメッキによる突起電極形
成後、メツキレシスト5を除去し、共通電極層4を除去
した場合を第2図に示す。次に熱処理により溶けた半田
がCW 層6上に丸まり半田突起電極8が完成する。こ
の共通電極4tエツチング等で除去する場合、シリコン
基板1内でのエツチング時間のバラツキ、或いは残渣が
残らない様にエツチング?オーバーに行なうと一部のポ
ンディング電極2をエツチングしてしまい断線不良が生
じてしまう・これを防ぐため、従来はパッシベーション
膜3の開口部と突起電極8の根元部分の重なり゛量tを
充分大きくとっておく必要があった。tは一般的には1
5〜25μm程度である。The present invention focuses on this point and aims to:
The object of the present invention is to provide a method for forming protruding electrodes that eliminates the above-mentioned drawbacks and allows for micro-pitch formation.Next, the case of forming solder protruding electrodes on a semiconductor device will be explained using drawings as an example.Figs. 1 and 2. , Figure 3 is a sectional view of the main part showing the conventional example.
2 is a silicon substrate, 2 is a bonding electrode formed of Al wiring on the silicon substrate 1, and 3 is a passivation film with a portion above the bonding electrode 2 being open. Reference numeral 4 denotes a common electrode layer made of metal such as Cr, C, L, etc., and is formed on the silicon substrate 1 by evaporation or the like over the entire surface. 07t has the role of passivation M3, ensuring adhesion to the ponding electrode 2, and diffusion between the CtL layer and the At film, which is the ponding electrode 2. The CV film is suitable for forming protruding electrodes. 5 is metsukiresist, 6 is Cu plated several μm under the protruding electrode.
Layer 7 is Pb-8n H/D plated on the CtL layer 6 to a thickness of several tens of μm. After forming the protruding electrodes by this plating, the plating resist 5 is removed and the common electrode layer 4 is removed, as shown in FIG. Next, the solder melted by heat treatment is rolled onto the CW layer 6 to complete the solder protrusion electrode 8. When removing the common electrode 4t by etching or the like, is there any variation in the etching time within the silicon substrate 1, or is the etching done so that no residue remains? If this is done excessively, part of the bonding electrode 2 will be etched, resulting in disconnection.To prevent this, conventionally, the amount of overlap t between the opening of the passivation film 3 and the root of the protruding electrode 8 is set to a sufficient amount. It had to be kept large. t is generally 1
It is about 5 to 25 μm.
このため突起電極8の根元径りはパッシベーション開口
部の径d工り30〜50μm大きくする必要があり、突
起電極80間隔乞小さくする、即ちマイクロピッチ化を
困難にしていた。For this reason, it is necessary to increase the root diameter of the protruding electrodes 8 by 30 to 50 μm compared to the diameter d of the passivation opening, making it difficult to reduce the spacing between the protruding electrodes 80, that is, to create a micro pitch.
次に、第4図、5図、6図にて本発明の詳細な説明する
。Next, the present invention will be explained in detail with reference to FIGS. 4, 5, and 6.
メッキにより突起電極形成し、レジストを除去するまで
は従来と同じであるが、メツキレシストは若干薄めに形
成しておく。共通電極層は、下からAt% Cr s
Cu と形成し、At、−’ C,層を下層4h、C
tb 層を上層4αとする。まず、Cu、層のみを選択
的にエツチングするがメツキレシストが薄く形成されて
いると突起電極の半田メッキ部7と共通電極上層14α
の間隔ルが小さく液回りが悪く他の部分に比べて極端に
エツチングが遅い、そのため第4図に示す如く半田メッ
キ7層下側のみCu、層4αが残る。次にC,層14α
をマスクにして共通電極の下層14b即ちcr、ct層
をエツチングにて除去する。これが第5図に示す断面図
である。次に再度上層4αをエツチングで除去し熱処理
にて半田層を丸めると第6図に示す如く半田突起電極8
が完成する。この実施例では、半田突起電極8の根元径
と)(ツシベーション膜3の開口部の径はほぼ同じであ
る。即ち、共通電極を上層、下層に分けて選択エッチを
行ない再度上層をエツチングする事によりこれが可能と
なる゛。この方式によれハハンブ根元径t)(ツシベー
ショ/開口部の径より小さくする事も可能である。The steps from forming protruding electrodes by plating to removing the resist are the same as in the conventional method, but the resist is formed slightly thinner. The common electrode layer is made of At% Cr s from the bottom.
Cu, At, -' C, layer is formed as lower layer 4h, C.
Let the tb layer be the upper layer 4α. First, only the Cu layer is selectively etched, but if the metal resist is formed thinly, the solder plated portion 7 of the protruding electrode and the upper layer 14α of the common electrode are etched.
The spacing between the electrodes is small, and the liquid circulation is poor, and the etching is extremely slow compared to other parts.Therefore, as shown in FIG. 4, the Cu layer 4α remains only under the 7 layers of solder plating. Next, C, layer 14α
Using this as a mask, the lower layer 14b of the common electrode, that is, the CR and CT layers, is removed by etching. This is the sectional view shown in FIG. Next, the upper layer 4α is removed by etching again and the solder layer is rounded by heat treatment, resulting in solder protrusion electrodes 8 as shown in FIG.
is completed. In this embodiment, the diameter of the root of the solder protrusion electrode 8 and the diameter of the opening of the tushivation film 3 are almost the same.In other words, the common electrode is divided into an upper layer and a lower layer, selective etching is performed, and the upper layer is etched again. By using this method, it is also possible to make the diameter of the base of the shaft smaller than the diameter of the opening.
以上、詳述した如く不発明によれば)(ツシベーション
膜の開口径に関係なく突起電極の形成が可能となり従来
200μm以下のピッチでは形成困難であった突起電極
が、100μm以下でも可能となりデバイスの微細化に
対応した突起電極のマイクロピッチ化が可能となる。又
、突起電極の根元径を小さくする事によりシリコン基板
の突起電極形成部に集中する堆積応力或いは熱応力が緩
和されデバイスの品質が向上する等の多大な効果を有す
る・As described above, according to the invention, it is possible to form protruding electrodes regardless of the aperture diameter of the tsusivation film, and protruding electrodes, which were previously difficult to form at a pitch of 200 μm or less, are now possible to form devices with a pitch of 100 μm or less. It is possible to make the protruding electrodes micro-pitched in response to the miniaturization of the protruding electrodes.In addition, by reducing the root diameter of the protruding electrodes, the deposition stress or thermal stress concentrated on the protruding electrode forming portion of the silicon substrate is alleviated, which improves the quality of the device. It has great effects such as improving
第1図・第2図、第3図は従来の突起電極形成法を示す
要部断面図、第4図、第5図、第6図は本発明の突起電
極形成法を示す要部断面図である。
1・・・シリコン基板、
291.ポンディング電極、
3・・・パッシベーション膜、
4・・・共通電極、
4α・・・共通電極の上層、
4b・・・共通電極の下層、
8・・・突起電極。
第1図
第4図
ワFigures 1, 2, and 3 are cross-sectional views of main parts showing the conventional method for forming protruding electrodes, and Figures 4, 5, and 6 are cross-sectional views of main parts showing the method for forming protruding electrodes of the present invention. It is. 1... Silicon substrate, 291. Ponding electrode, 3... Passivation film, 4... Common electrode, 4α... Upper layer of common electrode, 4b... Lower layer of common electrode, 8... Projection electrode. Figure 1 Figure 4
Claims (1)
て密着性を保持し、メッキ形成を行うための共通電極層
を選択エツチング可能な複数の金属膜で形成し、該複数
の金属膜の上層を形成する第1の金属膜の一部を最初に
エツチング除去し、次に前記突起電極と第1の金属膜を
マスクとして下層を形成する第2の金属膜ンエッチング
除去し、再び前記第1の金属膜をエツチング除去する工
程とよりなることを特徴とする半導体装置の突起電極の
形成方法。A common electrode layer for plating is formed of a plurality of metal films that can be selectively etched to maintain adhesion during the formation process of the protruding electrodes that serve as input/output terminals of the semiconductor substrate. A part of the first metal film forming the upper layer is first removed by etching, then a second metal film forming the lower layer is removed by etching using the protruding electrode and the first metal film as a mask, and then the second metal film forming the lower layer is removed by etching. 1. A method for forming a protruding electrode for a semiconductor device, comprising the step of etching away the metal film of step 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57064802A JPS58182247A (en) | 1982-04-20 | 1982-04-20 | Formation of projected electrodes of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57064802A JPS58182247A (en) | 1982-04-20 | 1982-04-20 | Formation of projected electrodes of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58182247A true JPS58182247A (en) | 1983-10-25 |
| JPH0328819B2 JPH0328819B2 (en) | 1991-04-22 |
Family
ID=13268732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57064802A Granted JPS58182247A (en) | 1982-04-20 | 1982-04-20 | Formation of projected electrodes of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182247A (en) |
-
1982
- 1982-04-20 JP JP57064802A patent/JPS58182247A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0328819B2 (en) | 1991-04-22 |
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