JPS589433B2 - Cursor control method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a cursor control method.

The increment mode is known as a method in which the entire screen (frame) is scanned in parts.

For example, in one frame, an even numbered rask is scanned for the first time, and an odd numbered rask is scanned for the second time.

This ink-lace mode is also used in CRT display devices for displaying images.

An example of this image display is shown in FIG.

In image display, the screen can be displayed pixel by pixel, and even-numbered pixels counting from the top of the screen are displayed as even-numbered lines,
Odd-numbered pixels are called odd-numbered lines.

A pixel consists of vertical and horizontal dots, generally m×n dots.

In the figure, m-11 and n are arbitrary. A rask address is set for each line, and m = 11 in the figure, so
One pixel is composed of 11 rask addresses.

Furthermore, in the figure, the character "E" is displayed as a display character on consecutive even and odd lines.

In the display example shown in FIG. 1, one screen is first scanned for even rask addresses (even field), and then scanned for odd rask addresses (odd field).

When both are completed, one scan of one screen is completed.

This method is one method of increase mode.

In the figure, the solid line shows the lanuta of the even field, and the dotted line shows the rask of the odd field.

However, the reason why the solid lines and dotted lines indicating the even and odd numbers of the rask address are different between the even and odd lines is that the rask address is displayed relatively for each line, and the rask address is actually Addresses are displayed absolutely.

That is, the 0th rask address on the odd line becomes the 11th rask address when viewed from the rask addresses on the even line, and the 1st rask address on the odd line becomes the 12th rask address.

Therefore, the solid lines and dotted lines can be shown in the figure.

In addition to the incremental mode shown in FIG. 1, there are various other methods.

That is, there is also the idea of an odd field rask and an odd field rask in the form of relative representation.

This case is based on the first incremental scan mode (ISV).
It is called I mode).

The example shown in FIG. 1 is referred to as ■SV2 mode.

There are various other methods. Let us now discuss the cursor display when such an increment mode method is adopted.

The cursor display is used to specifically indicate a part of the screen.

Examples of the indication format include an underline shape display and a block shape display.

The present applicant previously applied for a valid patent that allows the start and end of the cursor to be specified as addresses from the outside in order to enable the cursor display position to be set programmatically.

That is, this method provides a cursor star trask register and a cursor end rask register that can be set from the outside.

The start and end rask addresses of the cursor are set in these two registers.

Next, actual scanning is performed. In the process of this scanning, a match detection circuit provided separately checks whether the rask address matches the start and end rask addresses set above, and when a match is obtained, generates a timing signal, In this method, a cursor displayable (cursor enable) interval is set between the intervals in which timing signals matching the start and end timing signals are generated.

With this method, there is no particular problem when adopting a mode other than the incremental scan mode, that is, a non-increse scan mode that continuously scans rask addresses regardless of whether they are even or odd numbers, but under the incremental mode. A problem occurs.

Let me explain in detail.

In the case of ISV1 mode, cursor display is possible if the start and end register settings are set to even or odd numbers, but this results in a blind-like display.

For example, “0” in the cursor star trace register,
When the cursor end rask is set to "4", there is no cursor in the first and third rask.

On the other hand, in the ISV2 mode shown in Figure 1, the program value (
It is not possible to obtain a cursor display time signal corresponding to the value set in the register.

That is, it is not possible to obtain a cursor display shape that corresponds to the program value.

An object of the present invention is to provide a cursor control method that can be applied to both non-inklace and interlace scan modes (can display any cursor shape corresponding to programmed setting values).

The gist of the present invention is to compare the actual rask address with the contents of the start and end rask registers by comparing their sizes, instead of detecting a match as in the conventional example, and to compare the actual rask address with the contents of the start and end rask registers. This is designed to display a cursor.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2A is a diagram showing an embodiment of the present invention.

In the figure above, 1 is the cursor star trass register,
2 are cursor end scratches, each with 5
It has a bit configuration.

3 to 7, 8 to 12 are 1-bit comparators, and register 1
, 2 and each bit of the rask address RA.

All are negative logic.

The diagram clearly shows the input/output relationship of the block.

One bit of register output is 8, one bit of rask address is 100, and input from the previous stage is 2, A=BI, A>BI.
There are two outputs: A=BO and A>BO (however, the negative logic display follows the diagram).

1-bit comparators 3-7 are connected in series, and 1-bit comparators 8-12 are also connected in series.

FIG. 3 shows the internal configuration of the 1-bit comparator shown in the diagram.

The 1-bit comparator in FIG. 3 consists of NOR gates 30, 31, AND gate 32, inverter 33,
It consists of an OS) 34 and an E-MOS (drive MOS) 35.

X1 is applied to the inverting comparison input terminal 36; There is.

Terminal 38 has an A>B establishment signal, and terminal 39 has A = B.
, and the terminal 41 has the matching signal A=B of the corresponding bit.
A magnitude comparison signal A>BO of the corresponding bit is output to the terminal 42.

A detailed explanation of the operation will be omitted since it is obvious.

Return to Figure 2 A.

Each comparator constitutes a 5-bit digital comparator by connecting 5 stages in series.

Comparators 3 to 7 carry equal sign IJ −A=B to the lower bits.
While transmitting the O inequality carry A>BO, comparison operations are performed in order from the higher order, and the result is output from the lowest 1-bit comparator 7.

The same applies to comparators 3 to 7.

13 and 14 are AND gates for generating the cursor enable signal 19 from the comparator output.

Output 17 of gate 13 is A≧B establishment signal, output 18 is A
Indicates a ≦B establishment signal.

The NOR gate 15 inputs the signal 19, a blank signal 20A obtained by inverting the display section signal 20 through the inverter 16, and a cursor position signal 21, and generates a cursor video signal 22 as an output.

The operation will be described with respect to the ISV2 mode shown in FIG. 1, where the cursor star raster register 1 is set to "3" and the cursor end raster register 2 is set to "8".

A time chart for an even field in this case is shown in FIG.

The horizontal maximum character count signal is also the input clock for the raster counter.

The A≧B establishment signal 17 is at a high level only when raster address RA≧cursor end contents of the raster register (3), and the A≦B establishment signal 18 is when raster address RA≦cursor end contents of the raster register (8). Indicates high level only when .

Therefore, by taking the NAND of the signals 17 and 18, the desired cursor enable signal 1 is obtained as shown in FIG.
You can get 9.

Note that the blank signal 20A is for prohibiting cursor display during retrace time, and the cursor address match signal 21
The signal is also input to the NOR gate 15, and a cursor video signal 22 is obtained.

As described above, the circuit configuration is simple and the number of gates in the 1-bit comparator cell can be relatively small, making it suitable for LSI implementation.

FIG. 5 shows another embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same reference numerals.

The difference from FIG. 2 is that the raster address SRA synchronized with the master side output of the raster counter is used as the raster address, and a T latch circuit 23 is added.

This operation will be explained using the time chart of FIG.

However, the set date to the register is the same as in FIG. 4.

Sl{A is the maximum number of characters signal (raster crank) from RA
Since the phase is advanced by the pulse width, the cursor enable signal 24 is also a signal that is advanced by the pulse width compared to the case of FIG.

By inputting the signal 24 to the T latch circuit 23 and latching it at the timing of the horizontal minimum character signal 25, the signal 2
5 is obtained (the horizontal minimum character signal 25 indicates the first character time timing in one raster period and has a pulse width of one character time).

Therefore, the delay of the cursor enable signal 19 from the fall of the horizontal maximum number of characters signal can be reduced, and speeding up can be achieved.

This has the effect of increasing the margin against delays due to wiring capacitance and gate capacitance within the LSI chip.

In each of the above embodiments, the case of the increment mode has been described, but the present invention can be applied to the non-increment mode.

Furthermore, the cursor can take various forms depending on the data set in both the start and end registers.

For example, if the start and end data are set to match, it becomes a point cursor, and if the start and end points of a pixel area are set as data, the entire corresponding pixel becomes a cursor display.

This means that the cursor display can be changed in various ways depending on external settings.

For example, software processing enables dynamic cursor display.

Furthermore, although a bit comparator is used in each embodiment, a configuration in which data comparison is performed by taking complement numbers is also possible.

According to the present invention, the cursor shape is programmed in accordance with the set values of the cursor star raster and cursor end raster registers in both non-inklace and interlace scan modes.

Therefore, since the same cursor control circuit can be applied to any raster scan type CRT display device, it is highly versatile and economical, and is suitable for LSI implementation.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the rask address and display screen in the incremental scan mode, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a circuit diagram supplementary to Fig. 2. , FIG. 4 is a time chart diagram illustrating the operation of one embodiment, FIG. 5 is a circuit diagram illustrating another embodiment of the present invention, and FIG. 6 is a time chart diagram illustrating the operation of another embodiment. be. 1... Cursor star raster register, 2...
...Cursor end raster register, 3 to 12.
...Bit comparator.

Claims (1)

[Claims] 1 The cursor start rask register to which the cursor start rask address value is written, the cursor end rask register to which the cursor end rask address value is written, and the actual rask address and the address values of the above start and end rask registers, respectively. A cursor control method is provided, comprising a comparison means for comparing sizes, and displays a cursor only when an actual rask address is between address values written in both registers.