JPS589486A - Synchronous detection circuit - Google Patents

Abstract

PURPOSE:To reduce the error of a byte synchronizing clock and at the same time to eliminate disorder of byte synchronism, by producing the byte synchronizing clock with use of a framing code and its preceding clock line. CONSTITUTION:The wave detection output of a wave detecting circuit 13 is supplied to a gate circuit 421, and at the same time a pulse P42 showing the signal period of the character broadcast is supplied to the circuit 421 as a control signal. A packet PCT is extracted out of the circuit 421. This PCT is supplied to a shift register 422 of the serial input and parallel output of 12 bits for example as well as to a PLL423. Thus a clock BITC having the bit synchronism is produced and supplied to the register 422. The AND circuits 424 and 425 plus an NOR circuit 426 are provided as decoders. The outputs QC-QL of the register 422 are supplied to the circuit 424; and the outputs QA-QK of the register 422 are supplied to the circuit 426. The outputs of the circuits 424 and 426 are supplied to the circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION In television broadcasting, teletext multiplex telecasting is being considered in which various types of information such as news, weather forecasts, notices, etc. are broadcast using the vertical blanking period of the main program.

This teletext signal is sent, for example, in a format as shown in FIG. In other words, as shown in FIG. 1, the signal for descriptive text broadcasting is transmitted during the 20th horizontal period (when it is an odd field period) and the 283rd horizontal period (when it is an even field period) in the vertical blanking period. It is sent serially, and one section of this signal is called a bucket) PCT, and this one bucket) PCT is
It consists of a 6-byte header section and a 31-byte data section.

This packet) PCT includes a page control packet PCP, a color code packet CCP, and a pattern data packet FDP as shown in FIG. has 2 bytes of clock run-in CR, 1 byte of framing code FC, and 3 bytes of other control signals. Furthermore, the bucket) POP has a program number, page number, etc. in the data section, the packet CCP has a color code to specify the color in the data section, and the bucket) FDP has one line of teletext image in the data section. It has 248 dots of data.

Also, as shown in FIG. 1E, the data section is black.

The frame-in CR is a signal in which 1'"h"o" are alternately followed, and the framing code PC is [72] to
This is the code signal corresponding to .

Then, these packets PCP, CCP, and PDP are combined in accordance with the display mode and sent sequentially.

Therefore, for teletext broadcasts in such formants,
The receiver is constructed, for example, as shown in FIG.

That is, in FIG. 2, (1 (1 indicates the video signal system, Uυ is the tuner, 04 is the video intermediate frequency amplifier, I3
1 is a video detection circuit, and during normal broadcast reception, the color video signal from the detection circuit Q3 is supplied to the video circuit α4) and converted into three primary color signals, which are then supplied to the color picture tube (field) through the switch circuit α9. A color image is played.

Further, (4) shows a microcomputer that controls the reproduction of teletext. That is, ta is a CPU for example 8-bit parallel processing, (231 is a RAM for a work area for receiving teletext, and these are connected through a data bus 24) and an address bus.

In addition, (7) shows a reproducing circuit for teletext broadcasting, and C (3 is 1
Banfa Memo IJ with capacity for packets, 434
), 35) indicate a display memory having a capacity for one page, memory C (4) stores pattern data, and memory (351) stores color codes.

Further, (41) indicates a keyboard, and this keyboard (4I) has a key (switch) for switching between a normal broadcast reception mode and a teletext reception mode, a page selection key, etc., and its output is an interface. (To)
The timing signal is supplied to the bus 0a through the bus 0a, and is also supplied to the timing signal forming circuit (43).
Consisting of a PLL, a counter, a logic circuit, etc., the video signal is supplied from the detection circuit αJ, and a synchronization pulse is supplied from the synchronization separation circuit (43). Signals, such as an address signal when writing to the memory (G) and an address signal when continuing the memory (B) and (To), are formed.Flags indicating the vertical scanning period and the vertical retrace period are also formed. , is supplied from this formation circuit (421 to the CPU (2υ), and a flag indicating the end of various processes is supplied from the CPU (2υ) to the formation circuit (4).

Then, the video signal from the detection circuit OJ is supplied to a shift register 01)K with an 8-pit serial and parallel output, and the packet is converted from a serial signal to a parallel signal every 8 bits. ) 02, and a pulse P42 which becomes "1" in the horizontal period (20th and 283rd horizontal period) when the packet is sent is taken out from the forming circuit (4), and this pulse P42 is supplied to the gate 0 side as a control signal, and the packet signal is sent to the data bus (24
1.

At this time, the pulse P42 is supplied to the CPU (2υ as a hold signal, and the CPUGυ is a hold signal), and the PCT is held in the horizontal period hold state.
is the switching gate) (4119K: □ is supplied as Gohakugo, and the address signal from 41 is the gate 0
6) is supplied to the memory G moat.

Therefore, the packet signals are transferred in parallel by 8 pins from the register H to the memory (to) via the gate circuit 03 and the data bus Q4, and are sequentially written into the memory.

Then, when the horizontal period of PCT (bucket) ends, P42-
'0''K, register Gυ is disconnected from the data bus by gate 03. Also, when the hold state of CPUI2υ is released, address bus Q51 is switched to connect memory (c) to K through (46). be done.

Next, the memory data is transferred to the CPU (by 2υ, the ROM (
It is processed according to 24 programs, and the keyboard (
41), it is determined from the page control signal whether it is the desired page inputted, and if it is not the desired page, it is ignored.

This operation is repeated for each field until the desired page bucket (PCT) is sent.

and the data in memory is a bucket of desired pages)
During PCT, the following operations are performed. That is, when a CCP (bucket) is sent, it is written to the memory (331) by DMA in the same manner as described above.

Then, the writing of this packet CCP is completed, and the CPU
(When the hold state of 2υ is released, the data in the memory (to) is processed by the CPU (21), the color code is continuously read out from the memory (c), and this is transferred to the data bus (2).
It is written into memory (Ha) through Xun. Note that this writing is performed during the same vertical retrace period, and the address bus 0
ω is connected to the memory 0Q through switching (47)'a-, and the CPU (21) specifies the address of the memory (to).

Furthermore, when FDP (bucket) is sent, this is also DM.
A writes to the memory (c), then the CPU (2
By the process 1), only the pattern data is transferred from the memory (c) to the memory (b) K during the vertical retrace period. Note that the address specification of this memory 04) is also performed by the CPU (21).

When the packets CCP and FDP of the desired page are sent in this way, they are stored once in the memory (to) by DMA, and then only the necessary data is stored in the memory c+4) and the OS by the CPU (7) (21). transferred and written.

Then, the data of the last packet of the desired page is transferred to the memo IJ C341.
21) again enters the standby state for the desired page.

On the other hand, during the vertical scanning period, a control signal is supplied from the formation circuit (4) to the switching gate (4η, and an address signal from the formation circuit (4) is supplied to the memory C3L (351) through the switching gate (47) and (31), (
Three color codes and pattern data are sequentially output simultaneously.

The pattern data continued from the memory C3S is transferred to an 8-bit parallel input serial output shift register (36 bits).
), the parallel signal is converted into a serial signal, and this serial signal is supplied to the color generator 13n FC, and the color code successively read out from the memory (34) is supplied to the color generator (371) as a data signal. are three primary color signals, and this signal is supplied to the switch circuit 0ω.At this time, a control signal is supplied from the forming circuit (421) to the switch circuit (15+), and the switch circuit ttS is switched to the generator (371 side).

(8) Therefore, the desired page of teletext is displayed on the picture tube (16).

As described above, the television receiver shown in FIG. 2 receives teletext.

By the way, the above-mentioned clock run-in CR is used for bit synchronization, and the framing code F'C is used for byte synchronization (frame synchronization).

However, in this case, the data of the packet PCT may have the same bit arrangement as the framing code FC: 1:, "l", "0". Of course, the packet PCT is devised so that this false 7-raming code does not occur during normal reception. However, noise etc. may cause bit errors, which may result in false 7-raming codes.

If a false framing code is generated in this way, byte synchronization will be disrupted.

This invention attempts to solve these problems.

An example of this will be explained below.

In Figure 3, the detection output of detection circuit 0 is output from the gate circuit (
421), a pulse P42 indicating the teletext signal period is supplied to the gate circuit (421) as a control signal, and the gate circuit (421) outputs the packet PC.
T is peeked out. Then, the PCT may be a 12-bit series/parallel output shift register (
422) and pl, L (423) to form a bit-synchronized clock 1 (ITC), which is supplied to the register (422).

And the AND circuit (424), (4
25) and a NOR circuit (426), and the AND circuit (424) receives the outputs Qc and QF of the register (422).
, QG, QH, QJ.

QL is supplied, and the outputs QA, QB, QD, Qo, Q1 . Q.K.
is supplied.

K, these AND circuits (424) and NOR circuits (426
) is supplied to the AND circuit (425).

According to such a configuration, either the packet PCT or the register (
422) and is also shifted in the register (422), and as shown in FIG. , clock run in C
The last 4 bits of R 1010 and the framing code F
When C is supplied, the outputs of the AND circuit (424) and the NOR circuit (426) both become "L", and therefore, at this time, the byte synchronous clock BYCL is obtained from the AND circuit (425).

According to this invention, the framing code F
C and the clock run-in CR located before it are used to form the byte synchronized clock Byct,y. In other words, in the above example, 12 bits are used to form the byte synchronized clock BYCL. Therefore, compared to obtaining the byte synchronization clock BYCL from the 8-bit framing code i;"cff, there are significantly fewer errors and almost no disturbance in byte synchronization. Moreover, the configuration for this is simple. .
1

[Brief explanation of drawings]

Figures 1 and 2 are diagrams for explaining this invention;
The figure is a system diagram of an example of this invention. (422) is a shift register, and (423) is a PLL.

Claims (1)

[Claims] In a circuit that obtains a clock for frame synchronization from a serial data signal having a clock run-in left for bit synchronization at the beginning of the data section, and following this clock run-in, a seven framing code for frame synchronization of the data section. ,
The serial data signal is supplied to a serial input parallel output shift register, and the output of this shift register is supplied to a decoder, and a predetermined number of bits on the end side of the clock run-in and the framing code are obtained in the shift register. The synchronization detection circuit is configured to decode this in the decoder and obtain the clock for the frame synchronization from the decoder when the frame is synchronized.