JPS5895457A - Dual system switching control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual system switching control device, particularly a first switching control device used for controlling an electronic exchange. @! Regarding a device for controlling operation/standby switching of a central processing unit, the purpose is to provide a device that is easy to manufacture and provides stable operation.

The conventional device is shown in Figure 1.
central processing unit [hereinafter referred to as 1st. referred to as the second CPU],
(1) (4) is the first. The second CPU (1) (phantom driver receiver for each bus signal, i6) is a switching control device, and the extended first CPU (6) is a switching control device. Second CPU (
! ) bus, (7) is the external 4Atl! t, +81 is 1tflll interposed between the bus (6) and the external device (7)
1111 interface circuit. (9) and (2)
are the first. The signal lines a and (2) representing the operating status of the second CPUtl) and 12) (normal/failure) are the signal lines (to ) is a connection line between the control interface (8) and the external device (7).

In the conventional device, the switching control device vIL16) is connected to the signal line
.

Monitor the ring (C first, second CPU 11) (2)
When a failure is detected in one of the active CPUs, the CPU's driver-receiver, which was previously in the active system, is disabled, and the CPU's driver-receiver, which was previously in the standby system, is given permission to operate and switched to the active system. This is the method. However, the bus signals of the X, 2nd CPU'+1) (R) operate at a very high speed, and the control interface M (II)
Connecting fl'1 with a cable etc. involves great technical difficulties such as mutual interference between bus signal lines.
Very sophisticated manufacturing techniques are required to obtain sufficient stability.

Therefore, the present invention is directed to the first aspect. The bus of the second central processing unit is connected to the operation/standby switching means through the control interface, respectively, so that the first. This embodiment avoids the problem of interference between the buses of the second central processing unit.An embodiment of the present invention will be described below with reference to the drawings. Components having the same functions as those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

nws, t respectively t's@1, 2nd (7) CP
U (1) (respectively, the control interface f path connected over a short distance, ＠) is the control signal bus of the control interface circuit a4oIS, and (to) is the control signal bus Sakaki, which connects the external device (η) to the control signal bus. Or, each switch connected to (b) has @1 and @2 CPUs 11) +
2) is a signal line that indicates whether or not it is mounted, and is at logic level @"L" in the mounted state, and at logic level ""H" when it is not mounted. (2) is the switching control device, The signal line QO and the signal line @Z are monitored and a signal instructing switching of the switch (1) is outputted via the switching control line (2).

In this configuration, the first. @2 CPU
(1) The operating status of (2) is set by connecting the signal line (9) (to) to lR.
The switching control device (2) corresponds to the switching control device (5) in Figure 1.
) is the same as the conventional example shown in FIG. 1, but the overall configuration is different, so the configuration will be explained in more detail along with its operation.

Switching 11 n device: The outline of 1 (2) is that the operating system CPU
For example, if the CPU II) fails,
Connect the control signal bus signal output from the control input face circuit o4 on the CPUtl side of #il, which has been the active system, to the connection line shaft, and connect the switch to the control signal bus [phase]. The C control signal bus (b) is connected to the connecting line (2).
), and a specific example of this switching control device (2) is shown in Figure 8. @ is a manual changeover switch, and @ is a monostable multivibrator, which outputs a 1g pulse P1 every time the manual changeover switch is operated. (2) is a negative logic NAND gate, II4 (2
) - is a positive logic AND gate, 4 (to) is a filter circuit that properly translates one of the two inputs, (goods) is an inverter, (to) is a D-type flip-flop with a preset function and a clear function, Q is a positive logic NOR gate - is a power-on clear circuit, which generates one pulse P when the power is turned on. In addition, here @1. Depending on the operating status of the CPU (1) and (2), both CC pre-signal lines and ) loops are inverted to logic levels 1L and 1L and 1H respectively during normal operation and failure, and switch control is performed. Switching 1IoI connects the control signal bus So and the connection line (2) when the device is at logic level ``H'', and the switching control line -
When the logic level is "L", the switch (2) connects the control signal bus I and the connecting wire.

Now, when the power is turned on with the signal lines (@) and Qlm both at 1L, a pulse P! is sent from the power-on clear circuit.
occurs. Signal line area 9) Since @ are both 1L", the output of the gate) is inverted to 1H", and when pulse P2 is generated, the gate (goods) is pulse P, only the output of the gate is inverted to H", and the gate output is inverted to 1H". Hit the clear terminal CL of the flip-flop (to) through So, and output Q of the flip-flop (to).
becomes 6H" level and the connection line (B) becomes H" (
11) If both (2) are operating normally, the first CPU u will be set to standby mode when the power is turned on.
) becomes the operating thread, which is convenient for adjustments, etc.

In this state, the output of the gate circuit (2) is "L", and the selector circuit (2) outputs the signal lines +9), QG to the inverter 01) and the gate so, respectively. If both CPUs (1) and 21 are operating normally, the gate (c) output is H'', so the monostable multi-pibre threat ◆ changes to pulse P by operating the manual changeover switch (to).

occurs. This pulse Pl passes through the gate 'C
Hit the clock terminal CK of the flip-flop (to),
Then, the output q of the flip 70 is reversed to 6L" and the switching control line (2), which was at "H", is reversed to IIL", and the active system and standby system are switched. in this way,
If both CPUtt) (2) are operating normally, by operating the manual changeover switch (b), you can inspect the C control signal line, etc. by operating the manual changeover switch (b).

Next, when the first CPU (1) of the active system fails and the signal line (9) becomes "H", the output of the inverter 31) becomes 'H'.
"L", the preset terminal PR of flip 70 knob (to) is always set, and flip 70 knob (a) (7)
lti Force Q C is fixed at “L” °C Second CP
U (2) becomes the operational system.

Conversely, when the signal line (9) is 1L'' and the signal line - is H'', the output of the gate (2) becomes 1L'', the clear terminal of the flip-flop (2) is set, and the output Q becomes H”
CPUtt) of C'tR1 becomes the active system.

@1. 2nd CPUtt) If one of them fails, it will be repaired, but for example @1 CPUtt)
power; assuming it is repaired, the first CPU 1
1) is not installed and the signal line α becomes H". If in this situation, the CPU @2 fails further, the signal line (9
) remains at 1H", and the signal line (G) also becomes H".If we assume that the gate (E) does not switch the 94 wheels of the selector circuit, we can explain the operation of the flip-flop.
A set signal is input to both the preset terminal PR and the clear terminal CL, and the output Q becomes "H".
CPU (1) is selected, which is very inconvenient.

By the way, No. 1. The second CPU (1) (2) failed and
also generally attempts reprocessing; if the second CP
When Uf2> attempts to restart, it is inconvenient if it cannot connect to the external device. Therefore, in this embodiment, such a case is also assumed.

If the signal lines (9) - are both H'', the gate (2) detects it and outputs H'', -10,000, selector circuit @ ■
select the inputs of signal lines (2) and 4, respectively, so the H'' of signal line (6) is transmitted to the inverter (to) and sets the preset terminal PR of the flip-flop.

Therefore, the output Q4. t "L" and the $2 CPU on the implementation side (21 is selected. As a result, the
CPUt2+ can easily try restart processing.

Note that the above explanation is the same even when the signal line ring and (e) are exchanged.

As explained above, according to the present invention, the first
．． Since the second CPU and the control interface for the external device can be connected over the shortest distance, there is no fear of mutual interference between path signal lines as in the conventional case, and stable operation can be achieved. Also, on the output side of the control interface @1
．． The output side of this control interface is considerably slower than the output side of the second CPU. 2-(7) Since the CPU is switched, it can be manufactured at a lower technical level than the conventional configuration, leading to cost reduction.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional dual system switching control device, FIG. 2 is a configuration diagram of a dual system switching control device according to an embodiment of the present invention, and FIG.
The figure is a specific configuration diagram of the main parts of Figure @2. (1)...First CPU, (2)...Second CPU
PU, (7)...external device, (il)Oll-...signal line, Ql-...connection line-1...control interface circuit, a4@-...control signal bus, &a...switcher . @4...Signal line, (2)...Switching control device, (2)
...Switching control line agent Yoshihiro Morimoto Figure 1 Figure 2

Claims (1)

[Claims] 1. A dual system switching control device in which the buses of the 1.1Jj2 central processing units are respectively connected to operation/standby switching means via control interfaces. 2. Normally, the switching means causes a selector circuit to select a signal representing the operating state of the first and second central processing units. When one central processing unit fails, the other central processing unit is brought into operation, and when one central processing unit is not installed and the other central processing unit fails, the selector circuit is switched to a signal representing the installed state and the T71 block flop is controlled. 2. The dual system switching control device according to claim 1, wherein the dual system switching control device is configured to put the central processing unit 4+pupil being implemented into an operational state. 8. The switching means is connected to the first. 2. The dual system switching control device according to claim 1, wherein the dual system switching control device is configured such that the operating central processing unit can be switched by manual operation only when both the second central processing units are in normal operation. t. The switching means is connected to the first. Dual system switching control according to claim 1, wherein one central processing unit determined to be the active system is always set as the active system when the power is turned on only when both of the plurality of central processing units are in normal operation. Device.