JPS589608B2 - Circuit layout for threshold switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit arrangement for a monolithic integrated-degraded threshold switch, and the present invention relates to an input terminal of the circuit arrangement for a monolithic integrated-degraded threshold switch. A switch receives, for example, a DC voltage of variable magnitude from the output of a logic circuit and can produce at the output terminal of the circuit arrangement described above a specific switching current for driving a so-called 2L circuit, and A threshold switch consists of an arrangement of transistors, diodes, and ohmic resistors that are turned off at a constant lower threshold voltage and turned on at a higher threshold voltage.

Such threshold switches, or circuit arrangements comprising threshold switches in the form of monolithic integration, are known, and in the high state, e.g. MOS circuits, and in the low state, e.g. From a circuit arrangement that can produce a DC output signal of zO■ at the output terminal, a certain signal can be transferred to a certain circuit, that is, the so-called ■2, whose input can be substantially varied and yet requires a constant current input.
If it is necessary to supply the input terminals of the L-circuit, the aforementioned switches or circuit arrangements are included in such monolithic integrated circuits as so-called interface circuits.

Therefore, it is necessary to drive such a 12L circuit as specified, to prevent this circuit from being driven in the case of spurious signals, to be able to adapt it separately, and to ensure that the switching is always carried out in a reliable manner. There's a problem.

The hitherto known monolithic separated threshold switches are of the so-called fixed hysteresis type, which has to be adapted to a minimum operating voltage of, for example, 4 µ.

This is because otherwise the switching-on operation would become unreliable if the operating voltage fluctuated.

That is, when a certain signal, for example a voltage, appears at the output terminal of the MOS circuit, this known threshold switch turns on at a voltage of, for example, +3V and turns off again at a voltage of, for example, +IV.

This means that even for an operating voltage of +4V, for example +15V
This also applies for the operating voltage of , and also for the voltage variation range between these two limits.

In other words, even at an operating voltage of +15V, the turn-on operation is performed at +3■, and the turn-off operation is performed again at +IV.

However, in this case the switching range is only 2 mm, and the spurious signal can also be of this order of magnitude, so this spurious signal will limit the threshold, especially if the operating voltage is substantially larger than the switching range. This causes the switch to undesirably switch off.

The object of the invention is therefore to provide a circuit arrangement which avoids so-called fixed hysteresis, that is to say too narrow switching ranges, and always forms an optimum switching range, also called floating hysteresis, which is dependent on the operating voltage.

In order to solve this problem, in the threshold switch of the circuit arrangement according to the invention, the upper threshold voltage is located at a constant voltage distance UBE from the supply voltage, for example the accumulator voltage, and the said voltage is It is designed to maintain the voltage interval constant even if it fluctuates.

To this end, in the circuit arrangement that is the subject of the invention, the input terminals of said circuit arrangement are connected to the emitters of two transistors forming a first current mirror, and furthermore a second current mirror comprising at least three transistors. mirrors, the emitters of these transistors are connected to a supply voltage terminal, the input terminal of the first current mirror is connected to a reference voltage point via a constant current source and the input of the second current mirror is connected via a first diode. terminal, and further comprising two series-connected first and second amplification transistors, the collector or first collector of the second amplification transistor being connected to the output terminal of the second current mirror; The base of the amplification transistor is connected to the collector or the first collector of the second amplification transistor via the second diode, and the remaining output terminal of the second current mirror is connected to the collector of the first amplification transistor and the second collector. It is characterized in that it is connected to the base of the amplification transistor, and the collector or the first collector of the second amplification transistor is coupled to the input terminal of the circuit arrangement.

Various measures can be taken in individual cases to extend the flexibility of the circuit arrangement described above.

Therefore, in implementing the present invention, the emitters of the first and second amplifying transistors connected in series are connected to the reference voltage point, and the second amplifying transistor is connected to the output terminal of the circuit arrangement. the first collector of the second amplification transistor is connected to the emitter of another amplification transistor, the collector of the another amplification transistor is connected to the reference voltage point, and the base thereof is connected to the reference voltage point. Preferably, it is connected to an input terminal of the circuit arrangement.

Further, in a preferred embodiment of the present invention, the emitter of the first amplification transistor is connected to a reference voltage point, the emitter of the second amplification transistor is connected to the base of another amplification transistor, and the emitter of the another amplification transistor is connected to a reference voltage point. can be connected to the reference voltage point and its collector connected to the output terminal of the circuit arrangement.

Furthermore, in a further embodiment of the invention, the first collector of the second amplification transistor can be connected to the input terminal of the circuit arrangement via a third diode.

Furthermore, in implementing the present invention, it is preferable that the base of the first amplifying transistor is directly connected to the output terminal of the first current mirror.

Furthermore, in a preferred implementation of the invention, the base of the first amplification transistor can be connected to the output terminal of the first current mirror via a second diode.

The invention further includes a third current mirror having first and second transistors, the second current mirror including another transistor, and connecting the base-emitter path of the other transistor to the second current mirror. connected in parallel with the base-emitter paths of three other transistors, the collector of said further transistor being connected to the collector of the first transistor of said third current mirror; the bases of the second transistors of the third current mirror, and the emitters of the first and second transistors of the third current mirror are interconnected and connected to the reference voltage point; The collectors of the two transistors can be arranged to be connected to the input terminals of the circuit arrangement.

This variety of different circuit arrangements can be used to solve the problems mentioned in the earlier part of this specification.

That is, the problem can be solved by providing floating hysteresis, and in fact, by providing a W-side input interference suppression circuit of the next-stage 2L circuit.

The reason for this is that a large number of spurious pulses in the form of a hum voltage that vary around a DC value of +4 cm no longer act continuously on the threshold switch and effectively press the barrier.

Examples will be described below with reference to the drawings.

Figure 1 shows two diagrams, the upper one being for example MO
This voltage represents the output voltage of the S circuit and is designated by U.

As a function of time, this voltage approaches the value UBH, which value corresponds to the so-called high voltage at the output terminal of the MOS circuit.

According to the invention, this voltage is separated by a voltage interval UB from the accumulator voltage.
You need to separate it by E.

As long as this voltage maintains the above-mentioned value, the threshold switch connects the turn-on state, which is represented by the current level ■A shown in the form of a square wave in the lower diagram.

Again the voltage decreases and finally reaches the value UR as a function of time
Reach L.

This value is also spaced from zero voltage by a voltage interval UBE.

At this point the switch is turned off again.

When the storage battery voltage UB changes, the upper value UEH always follows the fluctuation of the storage battery voltage.

Therefore, this upper value is from the storage battery voltage UB to the voltage interval U
Since it always remains at BE, we get what is called follow-on hysteresis.

In this case, the threshold potential point UEL below the voltage interval UBEO point from zero voltage is maintained.

The known monolithic threshold circuits already mentioned operate according to a fixed hysteresis, with the lower switching point and the upper switching point being at a fixed potential.

The monolithic integrated degraded threshold circuit of the embodiment shown in FIGS. 2-6 exhibits optimal hysteresis over a wide operating voltage range.

For example, the transistor T6 becomes conductive at the input voltage of the input terminal E which is smaller than the voltage UBE, and the diode D is cut off.

As a result, as is clear from the embodiment of FIG. 1, transistor T7 is turned off and transistor T8 is turned on.

In this case, a current may flow through the output terminal A.

Note that transistor T8 is inverted.
A multi-collector transistor can be obtained by forming an NPN structure.

When the input voltage at the input terminal E increases to a certain value UB-UBE, the first current mirror circuit comprising the transistors T1 and T2 is activated and the transistor TI supplies the base current.

As a result, transistor T8 is cut off and no current can flow through output terminal A.

A second current mirror circuit comprising a current source or transistors T3, T4 and T5 provides a supply current for the circuit arrangement.

The magnitude of this current is controlled by a constant current source IO.

In its simplest form, this current source may be a resistor of several hundred ohms, for example.

Diodes D1 and D2 determine the upper and lower switching threshold voltages.

This point will be explained again using the calculations below.

Further, the required input current can be calculated by the calculation described below.

As is clear from the calculation results described below, the circuit arrangement shown in FIG. 3 requires a larger input current than the circuit arrangement shown in FIG.

The circuit layout shown in FIG. 4 is a combination of the circuit layouts shown in FIGS. 2 and 3.

This circuit arrangement has the same hysteresis characteristics, but this circuit arrangement has a lower input current for the upper switching threshold voltage as in the circuit arrangement shown in FIG. 3 and a lower input current as in the circuit arrangement shown in FIG. Requires input current of side switching threshold voltage.

The circuit layout shown in FIG. 5 is a combination of the circuit layouts shown in FIGS. 2 and 3.

This circuit arrangement has an input current for the upper switching threshold voltage as in the circuit arrangement shown in FIG. 2 and an input current for the lower switching threshold voltage as in the circuit arrangement shown in FIG. and requires.

The circuit arrangement shown in FIG. 6 has the same input conditions as the circuit arrangement shown in FIG. 2, and can obtain an output current larger by the BN factor.

For convenience of explanation of the following calculation example, symbols are defined as follows.

Let UBET2, UBET5, UBET6, and UBET7 be the base-emitter voltages of the husband transistors T2, T5, T6, and T7.

Let UA K D 1 and UA K D 2 be voltages between both terminals of diodes D1 and D2, respectively.

IOTt + IOT2fuI OT3νICT49■C
T5 is replaced by transistors TI, T2, T3, T4, T, respectively.
The collector current is 5.

IBT3 and IBT7 are transistors T3 and T, respectively.
? Let the base current be

Furthermore, let IDt be the current of the diode D1.

If Early effects are ignored, the circuit arrangement shown in FIG. 2 provides an upper switching threshold voltage UBH.

That is, UEH””UB UBBT5 UAKD1
+UBT2.

For monolithic integrated circuits, UBET5”UAK
Dt”:;UBET2:UBE, so the above formula is [JEH:TJB UBE+UBF, UBEUE
H”=UB−UBE.

Next, considering the lower switching threshold voltage, UEL=UBBT7+UAKD2-UBET6, so if UBET7'':'UAKD2''; UBETa=UBB, it can be seen that UEL=UBE.

Therefore, the hysteresis is ΔUE='[JEH-URL ΔUE=UB UBET5 UAKD1+UBET2
-(UBET7+UAKD2-UBET2)? UBET5 ”;UAKDt;UBET2=UBET7
If "UAKD2" UBET6=UBE, ΔUE=UB-2UBB.

Current IE at the upper switching threshold voltage when T I = T2 and T3 = T4 = T5
Hpa IOTI IOT2 IEH=IOTt +IOT2+ ” Tona BP
BP Ru.

If I OT 1= I GI’2, then 1 IBH=2 IOT2( 1+-) B.P. becomes.

Note that BP is the forward current gain of the PNP transistor.

Therefore ? OT3 It is.

IcT2- and IcT2=■BT7BN ■DI And further, if IOT3=, then 3 1+ RT) Therefore ? Become.

If we calculate IO from the formula for IOT2 mentioned above, we get 2IOT2 ■0: IDt +IOT2+ BP, which is the IC of this formula! Substituting T2 with the above-mentioned IDt formula and solving for ID+, substituting this into the IEH formula obtained earlier, multiplying the denominator and numerator of this formula by BN, we get:

Here is the forward current gain of the BN/NPN transistor.

If Bp=5 and BN=70, ■EH=0,2■o becomes.

Next, considering the current IEL required at the lower switching threshold voltage, it follows from both equations.

Here, BPV is the forward current gain of transistor T6.

This current LBL flows only during the switching phase and then becomes O.

When Bp=5, BN=70 and BPV=30, ■EL=0.02■o.

In the case of the embodiment shown in FIG. 3, if the Parley effect is ignored, the following results.

That is, the current required at the upper switching threshold voltage is IOTI IOT2 ■EH-IOT, + IOT2+- + -BP
It becomes BP.

In the case of IOT1=IOT2, the above formula becomes ■ IEO=2IOT2( 1+-) B.P. becomes.

Because it's not yet becomes.

Now, if 4T8 and IOTa are the first collector current and second collector current of transistor T8, respectively, * CT8 = CT1 + ICT4, so using the above relational expression, the other one is ICT8 - BN゜ICT3, If ICTs=IOT4, then ICTs=IOT4.

Regarding the switching point, it is as follows.

* ■CT8: ■CT8 Therefore, When we solve this for IDt and rearrange this equation, we get ■EH=1.69■o in this equation when Bp=5 and BN-70.

Next, considering the current IEL required at the lower switching threshold voltage, ■EL-■DT4 ICT4-IC! This is because when T3 and ICT3=IOT5.

This current L. EL flows only during the switching phase and becomes 0 thereafter.

In the case of Bp=5, the above formula is IEL =0.6 2 5 IQ becomes.

Although the above calculation example has been explained only for the circuit layouts of FIGS. 2 and 3, similar calculations can be performed for the embodiments of FIGS. 4, 5, and 6.

These calculations must be performed in a manner similar to that of the embodiments of FIGS. 2 and 3, and the method of operation thereof is as previously described.

The embodiment shown in FIG. 7 shows an example in which the input stage of the circuit according to the present invention is changed, and in this circuit arrangement, the transistor T
10, T11, and T12, the input terminal E
A specific output state (L-potential) is obtained with the circuit open circuit and no load.

The reason is that the collector current cT12 (~Io) is larger than the current IEL required for turn-off.

As a result of these steps, the current required for turn-on IBH
is increased by the amount of IO.

[Brief explanation of the drawing]

FIG. 1 is a curve diagram for explaining the operation of the threshold switch; FIGS. 2.3, 4, 5, 6 and 7 show various different embodiments of the threshold switch in monolithic integrated form according to the invention. FIG. E...Input terminal, T1-T12...Transistor, D1-D3...Diode, A...
...Output terminal, UB...Storage battery voltage (or its terminal), IO...Constant current source.

Claims (1)

[Scope of Claims] 1. For a monolithic integrated threshold switch that turns off at a fixed lower threshold voltage and turns on at a fixed upper threshold voltage, and whose size varies. a circuit arrangement with an input terminal E receiving a possible direct current voltage and an output terminal A capable of producing a specific switching current, said upper threshold voltage being located at a constant voltage distance from the supply voltage; The input terminal E of the circuit arrangement is connected to the emitters of two transistors T1 and T2 forming a first current mirror, in order to ensure that the voltage interval remains constant when the supply voltage varies due to the circuit arrangement. and at least three transistors T
3, T4, T5, the emitters of these transistors are connected to the supply voltage terminal UB, the input terminal of said first current mirror is connected via a constant current source IO to the reference voltage point and the second one diode D1 connected to the input terminal of said second current mirror;
a first and a second amplifying transistor T7, T8 connected in series, the collector or first collector of the second amplifying transistor being connected to the output terminal of the second current mirror; The base is connected to the collector or first collector of the second amplification transistor T8 via the second diode D2, and the remaining output terminal of the second current mirror is connected to the collector of the first amplification transistor TI and the second collector. Amplification transistor T
8 and the collector or the first collector of the second amplifying transistor T8 is coupled to the input terminal E of the circuit arrangement. 2. The first and second amplification transistors T? connected in series. , T8 emitters are connected to the reference voltage point,
Said second amplification transistor T8 has a second collector connected to the output terminal A of said circuit arrangement, said first collector of said second amplification transistor being connected to the emitter of another amplification transistor T6, said another amplification transistor T8 transistor T6
2. A circuit arrangement for a threshold switch according to claim 1, wherein a collector of the threshold switch is connected to the reference voltage point and a base thereof is connected to an input terminal E of the circuit arrangement. 3 Connecting the emitter of the first amplification transistor T7 to the reference voltage point, connecting the emitter of the second amplification transistor T8 to the base of another amplification transistor T9, and connecting the emitter of the another amplification transistor to the reference voltage point. A circuit arrangement for a threshold switch according to claim 1, characterized in that the collector is connected to the output terminal A of the circuit arrangement. 4. The circuit arrangement for a threshold switch according to claim 1, characterized in that the first collector of the second amplifying transistor T8 is connected to the input terminal E of the circuit arrangement via a third diode D3. 5. The circuit arrangement for a threshold switch according to any one of claims 1 to 4, characterized in that the base of the first amplification transistor TI is directly connected to the output terminal of the first current mirror. . 6. The threshold according to claim 1, wherein the base of the first amplification transistor TI is connected to the output terminal of the first current mirror via a second diode D2. Circuit layout for switch. 7 For monolithic integrated threshold switches that turn off at a fixed lower threshold voltage and turn on at a fixed upper threshold voltage, receiving a DC voltage that can vary in magnitude. a circuit arrangement with an input terminal E capable of producing a certain switching current and an output terminal A capable of producing a certain switching current, in which said upper threshold voltage is located at a constant voltage distance from the supply voltage and said circuit arrangement has said In order to maintain said voltage interval constant when the supply voltage varies, the input terminal E of said circuit arrangement is connected to the emitters of two transistors T1 and T2 forming a first current mirror, and furthermore at least three two transistors T
3, T4, and T5, the emitters of these transistors being connected to the supply voltage terminal UB, and the input terminal of said first current mirror being connected to a constant current source. is connected to the reference voltage point via the first diode D
1 to the input terminal of said second current mirror, further comprising two series-connected first and second amplification transistors T7, T8, the collector of said second amplification transistor or said first collector being connected to the output terminal of a second current mirror, and the base of the first amplification transistor TI is connected to the collector or the first collector of the second amplification transistor T8 via the second diode D2;
The remaining output terminal of the second current mirror is connected to the collector of the first amplification transistor TI and the base of the second amplification transistor T8, and the collector or the first collector of the second amplification transistor T8 is connected to the collector of the second amplification transistor T8. a third current mirror coupled to the input terminal E and further having first and second transistors, said second current mirror comprising another transistor T10 and connecting the base-emitter path of said other transistor to said second transistor; connected in parallel with the base-emitter paths of the other three transistors of the current mirror, the collector of said further transistor being connected to the collector of the first transistor T11 of said third current mirror; its base and the base of a second transistor T12 of said third current mirror, respectively, interconnecting the emitters of the first and second transistors of said third current mirror and connecting to said reference voltage point;
A circuit arrangement for a threshold switch, characterized in that the collector of the second transistor of the third current mirror is connected to an input terminal E of the circuit arrangement. 8. The emitters of the first and second amplification transistors T7 and T8 connected in series are connected to the reference voltage point, and the second amplification transistor T8 has a second collector connected to the output terminal A of the circuit arrangement. the first collector of the second amplification transistor is another amplification transistor T;
6, the collector of the another amplifying transistor T6 is connected to the reference voltage point, and the base thereof is connected to the input terminal E of the circuit arrangement. Circuit layout for short switch. 9 Connecting the emitter of the first amplifying transistor TI to a reference voltage point, connecting the emitter of the second amplifying transistor T8 to the base of another amplifying transistor T9, and connecting the emitter of the other amplifying transistor to the reference voltage point. 8. The circuit arrangement for a threshold switch according to claim 7, wherein the collector of the filter is connected to the output terminal A of the circuit arrangement. 10. Circuit arrangement for a threshold switch according to claim 7, characterized in that the base of the first amplifying transistor T7 is directly connected to the output terminal of the first current mirror. 11. The threshold according to any one of claims 7 to 9, characterized in that the base of the first amplification transistor TI is connected to the output terminal of the first current mirror via a second diode D2. Circuit layout for switch. 12 Connecting the first collector of the second amplifying transistor T8 to the input terminal E of the circuit arrangement via a third diode D3, and directly connecting the base of the first amplifying transistor T7 to the output terminal of the first current mirror. A circuit arrangement for a threshold switch according to any one of claims 7 to 9, characterized in that: 13 Connect the first collector of the second amplifying transistor T8 to the input terminal E of the circuit arrangement via a third diode D3, and connect the base of the first amplifying transistor T7 to the output terminal of the first current mirror. Claims 7 to 9 characterized in that the connection is made via a diode D2.
A circuit arrangement for a threshold switch according to any one of the following.