JPS5896766A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the semiconductor device enable to perform high speed action and enabled to form in high density by a method wherein a P<+> type layer and an N<+> type layer are provided at a part of a P type Si substrate, and a gate electrode is provided between both interposing an SiO2 film between them. CONSTITUTION:The P<+> type source 12 is held at zero potential, and the N<+> type drain 13 is made to have positive potential. Potential of the P type substrate is decided nearly by potential of the source. When the absolute value of the voltage of the gate electrode 5 is small, and no high concentration carrier region exists in the surface of the substrate, a thick depletion layer is generated at the junction of the substrate and the drain to make no drain current to flow. When a sufficiently negative voltage is applied to the gate electrode 5, and holes are stored in high concentration in the surface of the substrate, the drain current begins to flow. Moreover when a voltage higher than the threshold is applied to the electrode 5 to form an inversion layer of electrons in the surface of the substrate, the depletion layer is not extended, and the drain current can be controlled. The device thereof is not conducted completely up to generation of an avalanche or the tunnel effect of carriers, and indicates an ideal characteristic (a dotted line) without generating an weak inversion region as usual. However because the device is provided with no current limiting structure, it is necessary to insert a resistor in series.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel semiconductor device structure capable of high-speed operation.

MOS (MetalO
Due to its simple structure and relatively easy manufacturing process, it is widely used as a component of integrated circuits(1). A reduction has been created and an attempt has been made to speed up the operation.

FIG. 1 shows a schematic diagram illustrating the general structure and operation of a conventional MOS transistor. In FIG. 1, 1 is a semiconductor substrate having one conductivity type, 2 is an impurity-containing region having a second conductivity type different from the substrate 1, and 3 is the impurity-containing region 2.
4 is an insulating film formed on the substrate 1, and 5 is a gate electrode. In addition, in terms of an electric circuit, the impurity-containing region 2 is called a source, the impurity-containing region 3 is called a drain electrode, and 5 is called a gate electrode.

The operation of this MOS transistor using a P-type semiconductor substrate 1 will be explained as follows. Substrate 1 and source 2
is set to zero potential, and a positive voltage is applied to the drain 3. Now, if a negative voltage is applied to the gate 5 to prevent the formation of an inversion layer on the substrate surface, the surface of the semiconductor substrate 1 between the source 2 and the drain 3 will have a majority carrier (2) in the source and drain. Since there are almost no electrons, no current flows between the source 2 and the drain 3. Now, Kate 5
When a positive voltage higher than a threshold value is applied to the substrate surface 1 to form an inversion layer, a large number of electrons exist in the inversion layer, so a current flows between the source 2 and the train due to the movement of electrons. However, these two states do not change stepwise; instead, when the gate voltage is near the threshold, a weak inversion layer is formed on the substrate surface, and between the source 2 and drain 3. A current (drain current) that is limited to the number of electrons in the inversion layer flows. Thus, there is a weak inversion region where the drain current changes with changes in gate voltage.

Figure 2 shows the gate voltage (■
G) is a weak inversion characteristic of the drain X flow (log Ib). In Figure 2, the solid line is the characteristic of a conventionally structured MOS transistor, the dotted line is the characteristic of an ideal switching transistor, a is the region where leakage current flows at the junction of source 2 and drain 3, b is the weak inversion region, and ■T is the threshold. The value voltage C is a strong inversion region in which an inversion layer is formed in which a large drain current ML can flow. For the switching operation, three regions a and C are used, and b is essentially unnecessary. However, it is difficult to remove this in practice from OMOS
) As transistors become smaller and their operating voltage becomes lower,
Since the transition region S is not narrowed, the operating margins of each region a and C are narrowed. Therefore, it would be extremely effective to realize a characteristic (dotted line) in which no transition region exists.

The present invention eliminates the drawbacks of the conventional M 08 ) transistor and provides a new semiconductor device based on a new operating principle that enables high-speed operation and high density.

The gist is a semiconductor substrate and a portion of the surface of the semiconductor substrate.
a first high-concentration impurity-containing region having the same type as the substrate and a second high-concentration impurity having a second conductivity type different from that of the substrate provided on another part of the surface of the semiconductor substrate; The present invention provides a semiconductor device comprising a gate 'kt&' (4) provided on the surface of a semiconductor substrate between a containing region and the first and second high concentration carrier regions with an insulating film interposed therebetween. In this semiconductor device [1×L], the current flowing between the first and second impurity regions is controlled by applying a voltage of 1× to the gate electrode, and it does not have a transition region like the conventional structure. It becomes possible to realize the characteristics.

The operating principle of the present invention will be explained in detail below with reference to the drawings of the embodiments.

FIG. 3 is a schematic cross-sectional view showing one embodiment of the present invention.
In FIG. 3, the one shown in FIG. 1 and No. 1 is equivalent to that in FIG. 11 is a substrate partially having a mold, 12 is a first high-concentration impurity-containing region having the same conductivity as the substrate 11, and 13 is the ^# benign purity-containing region 1.
This is a second high concentration impurity-containing region having a second conductivity type different from No. 2. Two high concentration impurity containing regions 12.13
The impurity in the bonding with substrate 1 is I x 10'
%n-3 or more, it is desirable that the distribution be in the shape of a stem 7'. Isn't it easy to realize this?If you make a bond by ionizing/granting arsenic with a small diffusion constant on the surface of the substrate 1, Table 1 II Isoko I (5) Satisfy the Boko condition.The two high-concentration impurity-containing regions 12 and 13 are called a source and a drain, respectively.

The operation of this new semiconductor device using a P-type semiconductor substrate 11 is explained as follows. 1. The bias voltage (drain voltage) between the source 12 and the drain 13 is p
The source 12 is at zero potential so that the n junction is reverse biased.
The drain 13 is at a positive voltage.

Although no electrode is connected to the substrate 1, its potential is determined approximately by the potential of the source 12. Now, assuming that the absolute value of the voltage of the gate electrode 5 is small and a high concentration carrier region of an accumulation layer or an inversion layer is not formed on the substrate surface, a thick depletion layer is formed at the p-n+ junction between the substrate 11 and the drain 13. Board 1
1, no current (drain current) flows between the source 12 and drain 13. On the other hand, if a sufficiently large negative voltage is applied to the gate electrode 5 to form a highly concentrated pore-stopping accumulation layer on the substrate surface, the junction between the accumulation layer and the drain 13 on the substrate surface is an isometric p+-n+ This junction (
6) A high electric field will result. When the width of this depletion layer is less than several tens of tens of meters, carriers can tunnel through this depletion layer, and even if the width of the depletion layer is larger than this, avalanche occurs and the source 12 and drain 13
Current will begin to flow between. Furthermore, when a voltage higher than the threshold voltage is applied to the gate electrode 5 to form an electron inversion layer with a high concentration on the substrate surface, the inversion layer and the drain 13
The junction at the substrate surface is formed between the source 12 and the inversion layer and becomes an isometric l)++-junction, and the depletion layer at the surface hardly spreads and this junction becomes a high electric field. As a result, similar to the junction between the storage layer and the drain 13 described above, avalanche or carrier tunneling occurs at this junction, and current flows between the source 12 and the drain 13. In this way, the drain current I can be controlled by the gate voltage.

Since the present invention is based on this principle, when avalanche or carrier tunneling occurs, no current flows at all, and the weak inversion class (7) region shown in Figure 2 does not exist, and the ideal shown in Figure 2 is avoided. Characteristics (characteristics close to point 111i can be obtained. However, since the semiconductor device according to the present invention does not have a mechanism to limit the current when the element is in a conductive state, it is necessary to use a resistor for limiting the current or a special price of the active device. It is desirable to insert a resistor in series.

The novel semiconductor device according to the present invention has the potential for miniaturization and high speed, but also has several other features not found in conventional active semiconductor devices. The first is that the operation is bipolar with respect to the gate voltage, the second is that it can be formed in the same process regardless of the conductivity type of the substrate, and the third is that the drain current flows due to avalanche or tunnel effect. The characteristics of drain current with respect to drain voltage are non-saturation characteristics.

Although the structure and operation of the semiconductor device according to the present invention have been described above using a P-type substrate, it is clear that the structure and operation of the semiconductor device according to the present invention can be similarly realized even when the substrate is an n-type substrate. It is also clear that the Mr. conductor device according to the present invention can be realized by using a thin film or thick film semiconductor instead of a semiconductor substrate.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional structure MO8 transistor,
1 is a semiconductor substrate having one conductivity type, 2 is an impurity-containing region having a second conductivity type different from that of the substrate 1, 3 is an impurity-containing region having the same polarity as the impurity-containing region 2, and 4 is a semiconductor substrate of the substrate 1; The insulating film formed thereon, 5, is a gate electrode. Figure 2 shows the weak reversal characteristics of the drain current with respect to the drain voltage of the conventional structure MO8) transistor, the solid line is the characteristic of the conventional structure MO8)2 transistor, the dotted line is the characteristic of an ideal switching transistor, and a is the junction of the source and drain. The region where leakage current flows, b is the weak reversal region, VT is the threshold voltage, and C is the strong reversal region. FIG. 3 is a schematic cross-sectional view showing the first embodiment of the present invention. Items with the same numbers as in FIG. 1 are equivalent and have the same functions, and 11
12 is a first high-concentration impurity-containing substrate having the same conductivity type as the substrate (9) (10)

Claims (1)

[Claims] a semiconductor substrate, a first high-concentration impurity-containing region of the same type as the substrate provided on a part of the surface of the semiconductor substrate, and a first high concentration impurity-containing region of the opposite type to the substrate provided on another part of the surface of the semiconductor substrate. 1. A semiconductor device comprising: two high concentration impurity containing regions; and an electrode provided on the surface of the semiconductor substrate between the first and second high concentration impurity containing regions with an insulating film interposed therebetween.