JPS5896771A - Monitoring pattern for static induction type transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitor pattern for static induction transistors that can measure the substantial gate spacing.

In the manufacture of static induction transistors, the gate-to-gate spacing is an important parameter that determines values such as Idss and μ. As a monitor pattern for measuring this gate-to-gate distance, a punch-through type Di that utilizes a depletion layer of a PN junction has been used.

FIG. 1 is a sectional view showing a conventional punch-through type Di monitor pattern. In the figure, (1) is an N-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is a P-type diffusion layer forming a punch-through type Di part, (4) is a thermal oxide film, ( 5) is a metal wiring part (Al).

Next, the process of forming this monitor pattern and the case where this monitor pattern is used to control the diffusion depth and width will be described.

First, an N-type epitaxial layer (2) is grown on an N-type semiconductor substrate (1). After forming a thermal oxide film (4) on the same epitaxial layer (2) as the pattern of the static induction transistor, a hole is made in the punch-through type Di part using photolithography, and a P-type thick conductive film is formed. An impurity such as boron is diffused to form two pairs of PN junctions.

The P Juya diffusion layers formed in this way (3), (3
) When a voltage is applied between the layers, one depletion layer expands, and breakdown occurs when the depletion layer reaches the other conductive layer. This has a correlation with the spacing between the P-heavy diffusion layers, and is used as a monitor to control the diffusion depth a.

However, in the monitor pattern of a conventional static induction transistor, the punch-through WDi part has a curved edge of the gate diffusion part, so the area where the P-type diffusion layer spacing is narrowest, that is, the surface part of the P heavy diffusion layer, is punched. This method had the disadvantage that it was only possible to measure the voltage when the voltage passed through, making it impossible to completely monitor the pinch-off portion at the bottom of the source of an actual electrostatic induction transistor and the effects of source diffusion.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a monitor pattern for a static induction transistor that can measure the pinch-off portion under the source of a static induction transistor and also monitor the diffusion of the source itself.

In order to achieve such an object, the present invention provides a diffusion layer having the same diffusion width, the same conductivity type impurity, and the same diffusion depth as the source diffusion layer between the diffusion layers forming the punch-through type Di part. This will be explained in detail below using examples.

FIG. 2 is a cross-sectional view showing one embodiment of the monitor pattern of the static induction transistor according to the present invention, and FIG. 3 is a plan view showing the monitor pattern (only the diffused portion) seen from above the semiconductor substrate in FIG. It is a diagram. In these figures, (6) is the N-type diffusion layer corresponding to the source diffusion region, (
The force is applied to the metal wiring section (8) connected to this N+ diffusion layer (6).
) is a bonding butt part connected to the P+ type diffusion layer (3) and for measuring the punch-through t pressure of the bunch-through type D1 part.

Next, the process of forming a monitor pattern and the case where this monitor pattern is used as a monitor for measuring the actual gate interval will be described. First, an N- type epitaxial layer (2) is grown on an N++ semiconductor substrate (1). After forming a thermal oxide film (4) on the same epitaxial layer (2) as the butter of the electrostatic induction transistor, a hole in the punch-through type Di part is made using photolithography technology. An impurity having a property, such as boron, is diffused to form two pairs of PN junctions. Then, between the P+ type diffusion layers (3) and (3), for example, an N+ type scattering layer 6) having the same diffusion width and the same diffusion depth as the source diffusion part and having the same conductivity type impurity is formed. . When a voltage is applied between the P+ type diffusion layers (3) and (3) formed in this way, a depletion layer grows on one side, and breakdown occurs when the depletion layer reaches the other conductive layer, but punch A part of the punch-through of #-WDI can only be punch-through through the region of this N-type diffusion layer (6). That is, the punch-through voltage between the P+ type diffusion layers (3) and (3) does not punch through at the outermost surface of the N+W+ diffusion layer (6). As a result, the interval between the pinch-off portions of the electrostatic induction transistor can be monitored based on the correlation with the punch-through voltage.

It can also be used to control the diffusion of the N1 diffusion layer (6).

In the above embodiments, an N-channel static induction type transistor has been described, but it goes without saying that the same can be applied to a P-channel static induction board transistor.

As explained in detail above, according to the monitor pattern of the static induction transistor according to the present invention, it is possible to measure the substantial gate-to-gate distance, and it is possible to completely monitor the influence of source diffusion. There is an effect that can be done.

[Brief explanation of drawings]

11.1 is a cross-sectional view showing a conventional punch-through type Di monitor pattern, FIG. 2 is a cross-sectional view showing an embodiment of a static induction transistor monitor pattern according to the present invention, and FIG. FIG. 3 is a plan view showing a monitor pattern (only the diffusion portion) seen from above the semiconductor substrate in the figure. (1)...N-type semiconductor substrate, (2)...N-
type epitaxial layer, (3)...P+ type diffusion layer, (
4)...Thermal oxide film, (5)...Metal wiring part, (
6)...N-type diffusion layer, (force...metal wiring part,
(8)...Bonding pad part. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] For measuring the gate-to-gate spacing of a static induction transistor, a diffusion layer with the same diffusion width, same conductivity type, and same diffusion depth as the source diffusion layer is placed between the diffusion layers forming the punch-through type Di part. A monitor button for a static induction transistor characterized by a layered structure.