JPS59100577A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, particularly a heterojunction which has a high electron mobility in a channel region, a low resistance connection region and a high-speed operation. Field effect transistor.

(b) Background of the technology Aiming to further improve the performance and cost performance of information processing devices, higher speeds, lower power consumption, and higher integration of semiconductor devices are being promoted. Gallium arsenic (G), which is much larger than (Si)
Many semiconductor devices using compound semiconductors such as aAs) have been proposed.

In a conventional semiconductor device such as 81 or QaAs, carriers move in a space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions, but if the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering by impurity ions increases, and carrier mobility decreases. limited by.

In order to eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated by a heterojunction interface, which increases the mobility of carriers, especially at low temperatures. Heterojunction field effect transistor (abbreviated as heterojunction PET)
There is.

In a heterojunction WPET, a heterojunction interface is formed between a non-doped semiconductor layer and an electron supply layer that has low electron affinity and contains impurities, and is formed near the heterojunction interface of the non-doped semiconductor layer. electron storage layer (
A two-dimensional electron gas) is included in the conduction path between the source electrode and the drain electrode, and the electron surface concentration of the electron storage layer is controlled by a voltage of 1P applied to the gate electrode.
Impedance control of the conduction path is performed.

fc) Prior art and problems In a heterojunction FET to which such selective doping is applied, an electron storage layer is formed as shown in the cross-sectional view of Fig. 1(a). There is a structure in which a non-Dog semiconductor layer is provided on the substrate side and an electron supply layer is formed thereon (hereinafter referred to as a normal type), and a structure in which a non-Dog semiconductor layer is provided on the substrate side and an electron supply layer is formed on the substrate side (hereinafter referred to as the normal type), and The structure is roughly divided into a structure in which a supply layer is provided on the substrate side and an electron storage layer is formed on a non-doped semiconductor layer provided thereon via a heterojunction (hereinafter referred to as an inversion type).

In FIGS. 1(a) and (b), 1 is semi-insulating Q a
A s substrate, 2 is a semi-insulating GaAs buffer layer, 3 is n-type aluminum gallium arsenide (AIGaAs)
The electron supply layer 4 is a non-doped GaAs layer, and is made of non-doped GaAsd4.
An electron storage layer (two-dimensional electron gas) 5 is formed near the heterojunction interface with the As electron supply layer 3. Furthermore, 6 is a gate electrode, 7 is a source electrode and a drain electrode, and 8 is a low resistance connection region that connects the source or drain electrode 7 and the electron storage layer 5.

Comparing the above two types of structures, 1 In the inverted type illustrated in FIG. 1(b), the source/drain electrode 7 side of the electron storage layer 5 is the GaAs layer 4, and This is more advantageous in reducing contact resistance than the A I Ga As layer 3 of the normal type illustrated in a).

However, in the heterojunction PET with the above-mentioned normal structure, the electron mobility of the electron storage layer (two-dimensional electron gas) of about 1×lOCcrl/V・sec can be easily obtained, whereas conventionally known In the I-port junction FET with the inverted structure, the electron mobility of the electron storage layer is I x 10' (cM
It has a serious defect in that the V-sec is only 3'g, and its characteristics are far inferior to heterojunction PET, which is characterized by a channel region with high electron mobility.゛(d) Purpose of the Invention Regarding a heterojunction FET having a structure in which an electron storage layer is formed through a junction, it is possible to eliminate the above-mentioned defects regarding the electron mobility of the electron storage layer and take advantage of the feature of low contact resistance. The object of the present invention is to provide a heterojunction FET with excellent characteristics.

(e) Structure of the Invention The object of the present invention is to provide an insulating or semi-insulating substrate, a first semiconductor layer containing a donor impurity formed on the substrate, and a first semiconductor layer containing a donor impurity formed on the first semiconductor layer. a second semiconductor layer having a higher electron affinity than the tenth semiconductor layer formed in contact with the first semiconductor layer;
The first semiconductor layer has a structure in which an electron storage layer is formed by electrons transitioning from the first semiconductor layer to the second semiconductor layer via a heterojunction formed by the first semiconductor layer and the first semiconductor layer. The semiconductor layer is achieved by a semiconductor device in which a region in contact with the heterojunction is a region into which impurities are not introduced.

Heterojunction fi having an inverted structure that is the object of the present invention
In the FET, the reason why the electron mobility of the electron storage layer is significantly lower than that of a normal heterojunction FET as described above has not been previously known.

The present inventors have discovered that this decrease in electron mobility occurs in the n-type AlGaAs electron supply layer 3 in the conventional example shown in FIG. 1(b).
It has been found that this is due to the fact that donor impurities, such as silicon (Si) ions, have diffused into the electron storage layer 5.

An example of data confirming this fact is shown in Figure 2.

The sample used has a superlattice structure in which a normal type heterojunction is provided on an inverted heterojunction by sharing a non-doped Q a A s layer with the inverted hetero junction, and a shared non-doped G a
The thickness L of the As layer is varied in the range of IQ [nm] to 100) [nm]. The outer electron supply layer is formed of A Io, 3 Gao, y As, and is formed of Si through a non-doped spacer region of 6 [nm] from the heterojunction interface with the non-doped Ga As layer.
The concentration is limited to 1, and a sample with the same superlattice structure and no inverted Si doping is prepared as a comparison sample.

In Figure 2, the horizontal axis represents the thickness of the non-doped GaAs layer.

The vertical axis shows the electron mobility measured using the Hall effect. Curve A shown as a solid line shows the electron mobility of this sample (inverted two-dimensional electron gas and normal two-dimensional electron gas), and straight line B shown as a broken line shows the electron mobility of the comparative sample (normal two-dimensional electron gas). electronic gas).

While the electron mobility of the comparative sample without an inverted electron supply layer is constant as shown by straight line B, when an inverted electron supply layer is provided, the electron mobility decreases significantly from curve A. It is known that Furthermore, this decrease in electron mobility is considered to be due to the fact that St, which is a donor impurity in the inverted electron supply layer, has diffused into the non-doped Q a As layer.

Based on these results, inverted heterojunction FETs require a thickness greater than the normal type between the heterojunction interface, where the electron storage layer is formed by the two-dimensional electron gas, and the impurity-introduced region of the electron supply layer. It is necessary to provide a non-doped region with .

The effect of this non-doped region becomes clear when the thickness thereof is set to approximately 3Q (nm) or more from the data in FIG. 2 and the like.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

FIGS. 3(a) to 3) are cross-sectional views showing an embodiment of the present invention during its main manufacturing process, and FIGS. 4(a) and (b) show the composition ratio and introduction of the semiconductor substrate of this embodiment, respectively. FIG. 3 is a diagram showing the impurity concentration distribution obtained by
) and the same reference numerals indicate corresponding positions.

See Figure 3 (Ku) and Figures 4 (a) and (b).

On the semi-insulating GaAs substrate 11, non-doped Q a
As puff 77 layer 12, non-doped region 13a.

A consisting of n-type region 13b and non-doped region 13C
IGaAs electron supply layer 13, non-doped region r
4a and an n-type region 14b.
are grown epitaxially in sequence. Although the epitaxial growth method can be arbitrarily selected, in this embodiment, a molecular beam epitaxial growth method (MBB method) is used.

First, the GaAs buffer layer 12 is non-doped and has a thickness of 0.5 [μm] or more.

In this example, the AlxGa-xAs electron supply layer 13 has an AI composition ratio of X=0.3, as described above (
Consists of 3 regions 13a, b and C, the total thickness of which is 0.
．． 1 (11m) or more. Among these three layers, GaA
Non-doped region 13C forming a heterojunction with the s layer 14
is the characteristic area of the present invention, and its thickness is 30
(nm) to 5.9 [nm]. The region 13b in contact with this is doped with donor impurity Si in a doping amount of 1×1.
Thickness containing about 018 [cWv33, for example 20 [nm]
] is the electron supply region. Remaining non-doped region 13
a is a buffer region between the GaAs buffer layer 12 and the GaAs buffer layer 12;

The GaAs layer 14 is originally non-doped, and its AlGa
-Electron storage layer (2) near the heterojunction interface with the Ass layer 3
dimensional electron gas) 15 is formed. In addition, G a A
The effect of the depletion layer due to the surface level of the s layer 140 is the electron storage layer 1
It is necessary that the non-doped Ga
Since the depletion layer extends in the A s layer, in this example, Q a
A region 14b with a thickness of about 50 [nm] near the surface of the As layer 14 is doped with Si in an amount I x 1017 (cm-3:
Even if the total thickness of the non-doped region 14a and the n-type region 14b is about 0.2 [μm], the influence of the depletion layer due to surface states does not reach the electron storage layer 15. do.

Refer to FIG. 3(b), a step 19 is provided, and ions of Si, for example, are implanted into the source and drain electrode forming regions 18' of the G, aAs layer 14 to a depth reaching the AlGaAs layer 13 at a dose of about 5×10 [m+]. do.

Referring to FIG. 3(C), the mask 19 is removed and aluminum nitride (AIN), for example, is removed.
) is deposited on the entire surface to form the protective film 20, and then heat treatment is performed at a temperature of, for example, 750C ('C) for about 15 minutes to activate the implanted ions and increase the carrier concentration to, for example, 5X10'' (α- An NFI connection region 18 having a low resistance of about 3] is formed.

FIG. 3(d) After removing the reference protective film 20, gold/germanium/gold (A
Source and drain electrodes 1 by uGe/Au)
7 are respectively provided on the n-type connection region 18, and the gate electrode 16 is formed of, for example, aluminum (AI).

Regarding the present example described above, the electron mobility of the electron storage layer 15 was measured at a temperature of 77 (K) and was 30.000.
Results of about 50,000 to 50,000 (ffl/V-sec) were obtained, confirming the effectiveness of the present invention.

(g) As described in detail, according to the present invention, the electron supply layer is provided on the substrate side, and the electron mobility of the non-donor storage layer provided thereon is significantly improved, resulting in a heterojunction FET. An extremely high-speed semiconductor circuit can be formed by taking advantage of the characteristics of this structure, in which the characteristics of the present invention are fully exhibited and the ohmic contact resistance can be easily reduced.

[Brief explanation of drawings]

Figures 1 (a) and (b) are cross-sectional views showing conventional examples of heterojunction FETs, Figure 2 is a chart showing an example of the correlation between electron mobility and the thickness of the non-doped region, and Figure 3 (a). ) Regarding the cubic substrate, each composition ratio and impurity concentration buffer 7 layers, 1
3 is an AlGaAs electron supply layer, 13a is its non-doped region, 13b is an n-type region, 13c is a non-doped region, 1
4 is a GaAs layer, 14a is its non-doped region,
14b is an n-type region, 15 is an electron storage layer, 16 is a mate electrode, 17 is a source electrode and a drain electrode, and 18 is an n-type connection region. SaitU Sai2ml〉Doal　4= ShinnyylJ 3
m

Claims (1)

[Claims] (1) an insulating or semi-insulating substrate; a first semiconductor layer containing donor impurities formed on the substrate;
a second semiconductor layer having a higher electron affinity than the first semiconductor layer formed on the semiconductor layer in contact with the first semiconductor layer; semiconductor layer and K
Accordingly, the first semiconductor layer has a structure in which an electron storage layer is formed by electrons transferred from the first semiconductor layer to the second semiconductor layer via the heterojunction formed, and the first semiconductor layer A semiconductor device characterized in that a region in contact with a heterojunction is a region into which impurities are not introduced. A semiconductor device according to claim 1 characterized by: