JPS59109934A - digital input circuit - Google Patents

digital input circuit

Info

Publication number
JPS59109934A
JPS59109934A JP57218298A JP21829882A JPS59109934A JP S59109934 A JPS59109934 A JP S59109934A JP 57218298 A JP57218298 A JP 57218298A JP 21829882 A JP21829882 A JP 21829882A JP S59109934 A JPS59109934 A JP S59109934A
Authority
JP
Japan
Prior art keywords
circuit
input
information
digital input
fifo memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57218298A
Other languages
Japanese (ja)
Inventor
Yutaka Moriyama
裕 森山
Masahiro Tanaka
正宏 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57218298A priority Critical patent/JPS59109934A/en
Publication of JPS59109934A publication Critical patent/JPS59109934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/22Static coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To increase substantially the number of input points by executing a write in an FIFO memory circuit only in case when a state is varied, and reading successively an input information from the FIFO memory circuit by a read signal from a CPU. CONSTITUTION:An information inputted through an external input contact 1 and a filter circuit 2 is led temporarily into a state variation detecting circuit 4, and a detection of a state variation is executed. In case when the state variation is detected, a new information is written in an FIFO memory 6 by a write signal 5. In this state, a central processing circuit 7 can obtain an external information by reading the information in the FIFO memory 6.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、デジタル入力回路、特にマイクロプロセッサ
応用制御装置に使用される走査方式のデジタル入力回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital input circuit, and particularly to a scanning type digital input circuit used in a microprocessor application control device.

〔発明の技術的背景〕[Technical background of the invention]

マイクロプロセッサ応用制御装置のデジタル入力方式に
は、割込方式によるものと、走査方式によるものとがあ
るが、本発明は走査方式に関するものである。走査方式
のデジタル入力方法はソフトウェアの作9易さから多用
される場合が多いが従来の走査方式のデジタル入力回路
を第1図に示す。外部入力接点1の入力情報はフィルタ
ー回路2を経由し、バッファーダート回路3へ渡される
Digital input methods for microprocessor-applied control devices include those using an interrupt method and those using a scanning method, and the present invention relates to the scanning method. The scanning digital input method is often used because it is easy to create software, and a conventional scanning digital input circuit is shown in FIG. Input information from external input contact 1 is passed through filter circuit 2 to buffer dart circuit 3.

バッファゲート回路3は中央処理回路(CPU) 7か
らの読み込み信号によりそのダートを開き、情報を中央
処理回路7へ渡す。
The buffer gate circuit 3 opens the dart in response to a read signal from the central processing circuit (CPU) 7 and passes the information to the central processing circuit 7.

〔背景技術の問題点〕[Problems with background technology]

上記した方法によると中央処理装置は、外部入力接点の
最少動作時間内に走査完了しなければならず、外部入力
接点の数が多量の時には読み込みできないこととなる。
According to the above method, the central processing unit must complete scanning within the minimum operating time of the external input contacts, and cannot read when the number of external input contacts is large.

〔発明の目的〕[Purpose of the invention]

本発明は上記問題点を解決することを目的としてなされ
たものであり、走査方式のデジタル入力回路における外
部入力接点の点数制限を改良したデジタル入力回路に関
するものである。
The present invention has been made to solve the above-mentioned problems, and relates to a digital input circuit that improves the limit on the number of external input contacts in a scanning type digital input circuit.

〔発明の概要〕[Summary of the invention]

本発明では外部入力接点及びフィルタ回路を介して取込
まれた入力情報を一旦、状態変化検出回路へ導入し、状
態変化があった場合のみFIFOメモリ回路へ書込み、
CPUからの読込み信号によりFIFOメモリ回路から
順次入力情報を読み込むことにより実質的な入力点数を
増大させようとするものである。
In the present invention, the input information taken in through the external input contact and the filter circuit is once introduced into the state change detection circuit, and only when there is a state change, it is written to the FIFO memory circuit.
This is intended to increase the actual number of input points by sequentially reading input information from the FIFO memory circuit in response to a read signal from the CPU.

〔発明の実施例〕[Embodiments of the invention]

である。図中の符号、1.2および・3は第1図に対応
している。そして、外部入力接点1の入力情報が、フィ
ルター回路2を経由するまでは第1図の場合と同様であ
る。しかし、フィルター回路2を経由した情報は、状態
変化検出回路4へ一旦入力され、一定周期で状態変化検
出回路4内の旧情報との状態変化検出が実行され、ここ
で状態変化が検出された場合には、書き込み信号5によ
りPIF’0メモリー6へ新情報が書き込まれる。そし
て中央処理回路7はFIFOメモリー6内の情報を読み
込むことにより、外部入力情報を得ることができる。
It is. The symbols 1.2 and .3 in the figure correspond to those in FIG. The process until the input information from the external input contact 1 passes through the filter circuit 2 is the same as that shown in FIG. However, the information that has passed through the filter circuit 2 is once input to the state change detection circuit 4, and state change detection is performed at regular intervals with the old information in the state change detection circuit 4, where a state change is detected. In this case, new information is written to the PIF'0 memory 6 by the write signal 5. The central processing circuit 7 can obtain external input information by reading the information in the FIFO memory 6.

第3図は本発明によるデジタル入力回路の他の実施例構
成図である。図中の符号1ないし2、及び4ないし7は
第2図に対応する。本実施例では状態変化検出回路4か
らのFIFOの書込み信号5に中央処理回路7からの初
期化信号8を追加した例である。即ち、中央処理回路か
らの初期化要求によりFIFOメモリー6の内容を更新
することが可能であり、初期データーの読み込みを確実
に実行させることができる。
FIG. 3 is a block diagram of another embodiment of the digital input circuit according to the present invention. Reference numerals 1 to 2 and 4 to 7 in the figure correspond to those in FIG. In this embodiment, an initialization signal 8 from the central processing circuit 7 is added to the FIFO write signal 5 from the state change detection circuit 4. That is, the contents of the FIFO memory 6 can be updated in response to an initialization request from the central processing circuit, and initial data can be reliably read.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば走査方式のデジタル
回路に状態変化検出回路及びFIFOメモリ回路を付加
して中央演算処理回路へ導入するよう構成したので、全
情報を読み込む必要が々く、中央演算処理回路の走査周
期を長くすることが可能となりデジタル入力処理点数を
実質的に増大することのできるデジタル入力回路を提供
できる。
As explained above, according to the present invention, since the state change detection circuit and the FIFO memory circuit are added to the scanning type digital circuit and are introduced into the central processing circuit, there is no need to read all information, and the central It is possible to provide a digital input circuit that can lengthen the scanning period of the arithmetic processing circuit and substantially increase the number of digital input processing points.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の走査方式デジタル入力回路を示す図、第
2図は本発明によるデジタル入力回路の一実施例構成図
、第3図は本発明によるデジタル入力回路の他の実施例
構成図である。 1・・・外部入力接点   2・・・フィルター回路3
・・・バッファe−)回路 4・・・状態変化検出回路
5・・・書込信号     6・・・FIFOメモリー
回路7・・・CPU       8・・・初期化要求
信号(7317)代理人 弁理士 則 近 憲 佑(ほ
か1名) (5)
FIG. 1 is a diagram showing a conventional scanning type digital input circuit, FIG. 2 is a configuration diagram of one embodiment of the digital input circuit according to the present invention, and FIG. 3 is a diagram showing the configuration of another embodiment of the digital input circuit according to the present invention. be. 1... External input contact 2... Filter circuit 3
... Buffer e-) circuit 4 ... State change detection circuit 5 ... Write signal 6 ... FIFO memory circuit 7 ... CPU 8 ... Initialization request signal (7317) Agent Patent attorney Kensuke Noriyuki (and 1 other person) (5)

Claims (2)

【特許請求の範囲】[Claims] (1)入力接点を走査することにより順次入力情報を中
央演算処理装置へ取込むマイクロプロセッサ応用制御装
置のデジタル入力回路において、入力回路には入力情報
の状態変化を検出するだめの状態変化検出回路とFIF
Oメモリ回路とをそなえ、FIFOメモリ回路への書込
みは一定周期で行なわれる状態変化検出信号により行な
うと共に、中央演算処理装置への入力情報の取込みはF
IFOメモリ回路から行なうことを特徴とするデジタル
入力回路。
(1) In a digital input circuit of a microprocessor applied control device that sequentially inputs input information to a central processing unit by scanning input contacts, the input circuit includes a state change detection circuit for detecting changes in the state of input information. and FIF
Writing to the FIFO memory circuit is performed using a state change detection signal that is performed at regular intervals, and the input information to the central processing unit is input to the FIFO memory circuit.
A digital input circuit characterized by being operated from an IFO memory circuit.
(2)中央演算処理装置からの初期化信号によりFIF
Oメモリ回路のメモリ内容を更新することを特徴とする
特許請求の範囲第1項記載のデジタル入力回路。
(2) The FIF is activated by the initialization signal from the central processing unit.
2. The digital input circuit according to claim 1, wherein the digital input circuit updates the memory contents of the O memory circuit.
JP57218298A 1982-12-15 1982-12-15 digital input circuit Pending JPS59109934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57218298A JPS59109934A (en) 1982-12-15 1982-12-15 digital input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57218298A JPS59109934A (en) 1982-12-15 1982-12-15 digital input circuit

Publications (1)

Publication Number Publication Date
JPS59109934A true JPS59109934A (en) 1984-06-25

Family

ID=16717639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57218298A Pending JPS59109934A (en) 1982-12-15 1982-12-15 digital input circuit

Country Status (1)

Country Link
JP (1) JPS59109934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61169925A (en) * 1985-01-23 1986-07-31 Matsushita Electric Ind Co Ltd Operation switch circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587226A (en) * 1978-12-25 1980-07-01 Nec Corp Data processor
JPS5624628A (en) * 1979-08-08 1981-03-09 Nec Corp Keyboard control device
JPS5713534A (en) * 1980-06-27 1982-01-23 Casio Comput Co Ltd Key input buffer controlling system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587226A (en) * 1978-12-25 1980-07-01 Nec Corp Data processor
JPS5624628A (en) * 1979-08-08 1981-03-09 Nec Corp Keyboard control device
JPS5713534A (en) * 1980-06-27 1982-01-23 Casio Comput Co Ltd Key input buffer controlling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61169925A (en) * 1985-01-23 1986-07-31 Matsushita Electric Ind Co Ltd Operation switch circuit

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