JPH03260871A - Logic simulator - Google Patents

Logic simulator

Info

Publication number
JPH03260871A
JPH03260871A JP2061357A JP6135790A JPH03260871A JP H03260871 A JPH03260871 A JP H03260871A JP 2061357 A JP2061357 A JP 2061357A JP 6135790 A JP6135790 A JP 6135790A JP H03260871 A JPH03260871 A JP H03260871A
Authority
JP
Japan
Prior art keywords
logic
general
computer
logic arithmetic
simulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2061357A
Other languages
Japanese (ja)
Inventor
Toshiaki Tanaka
利明 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2061357A priority Critical patent/JPH03260871A/en
Publication of JPH03260871A publication Critical patent/JPH03260871A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To increase the processing speed of a logic simulator compared with a software simulator and to obtain the logic simulator at the hardware costs of a general-purpose computer and a logic arithmetic part by adding a logic arithmetic part for logic simulation to the general-purpose computer containing a CPU and a memory. CONSTITUTION:A general-purpose computer 1 containing a CPU 2 and a mem ory 3 is prepared together with a logic arithmetic part 4 connected to the com puter 1. The computer 1 carries out the processing except the logic arithmetic in the logic simulation and the logic arithmetic that is unable to be processed at the part 4. The part 4 is connected to the computer 1 and carries out the logic arithmetic for simulation under the control of the computer 1. The com puter 1 writes the logic arithmetic input into an input register and reads the logic arithmetic output out of a result register. If the computing speed of a logic arithmetic circuit is satisfactorily high, the relevant flow is executed with two instructions of the computer 1. Thus the logic simulation is carried out at a low cost and at a high speed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は論理シミュレータ、特に汎用コンピュータに論
理シミュレーション用論理演寡を実行する論理演算部を
付加し、論理シミュレーション実行速度を向上させた論
理シミュレータに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic simulator, particularly a logic simulator that improves the execution speed of logic simulations by adding a logic operation section to a general-purpose computer to perform logic operations for logic simulations. Regarding.

〔技術環境〕[Technological environment]

近年のIC技術の発展に伴い、大規模論理回路の設計が
非常に多くなり、論理シミュレーションにより論理を検
証しながら設計する事が多くなり、高速に論理シミュレ
ーションを実行する事が重要になってきている。
With the recent development of IC technology, the design of large-scale logic circuits has become very common, and the design is often performed while verifying the logic using logic simulation, and it has become important to perform logic simulation at high speed. There is.

〔従来の技術〕[Conventional technology]

従来の論理シミュレータは汎用コンピュータで、ソフト
ウェアにより論理シミュレーションを行うソフトウェア
論理シミュレータと、専用のハードウェアで論理シミュ
レーションを行うハードウェア論理シミュレータがあっ
た。
Conventional logic simulators are general-purpose computers, and there are two types: software logic simulators that perform logic simulations using software, and hardware logic simulators that perform logic simulations using dedicated hardware.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の論理シミュレータにおいては、ソフトウ
ェア論理シミュレータは、汎用のコンピュータが使用で
き、ハードウェアコストはかがらないが速度が遅く、ハ
ードウェア論理シミュレータは、速度は速いが専用のハ
ードウェアが必要でコストがかかるという欠点があった
Among the conventional logic simulators mentioned above, software logic simulators can be used on general-purpose computers and have low hardware costs but are slow, while hardware logic simulators are fast but require specialized hardware. The disadvantage was that it was costly.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の論理シミュレータの構成は、CPUとメモリを
含んで構成される汎用コンピュータと、前記CPUから
の制御により論理シミュレーション用論理演箕を実行す
る論理演算部とを含んで構威される。
The configuration of the logic simulator of the present invention includes a general-purpose computer including a CPU and a memory, and a logic operation section that executes logic simulation logic operations under the control of the CPU.

〔実施例〕〔Example〕

次に、本発明の実施例について、図面を参照して詳細に
説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。第
1図に示す論理シミュレータは、CPU2とメモリ3を
含んで構成される汎用コンピュータ1と、汎用コンピュ
ータ1に接続された論理演算部4を含んで構成される。
FIG. 1 is a block diagram showing one embodiment of the present invention. The logic simulator shown in FIG. 1 includes a general-purpose computer 1 including a CPU 2 and a memory 3, and a logic operation section 4 connected to the general-purpose computer 1.

汎用コンピュータ1により、論理シミュレーションのう
ち論理演算以外の処理と論理演算のうち論理演算部4で
処理出来ない論理演算を実行する。論理演算部は、汎用
コンピュータ1に接続され、その制御によりシミュレー
ション用論理演算を実行する。
The general-purpose computer 1 executes processes other than logical operations in the logical simulation and logical operations that cannot be processed by the logical operation section 4 among the logical operations. The logic operation unit is connected to the general-purpose computer 1 and executes simulation logic operations under its control.

第2図は第1図における論理演算部の一例である。汎用
コンピュータ1と制御バスa、アドレスバスb、データ
バスCで接続される。アドレスデコーダ5は、制御バス
aとアドレスバスbに接続され、入力レジスタ書き込み
信号dと出力マルチプレクサ選択読み出し信号eを出力
する。
FIG. 2 is an example of the logic operation section in FIG. 1. It is connected to a general-purpose computer 1 via a control bus a, an address bus b, and a data bus C. Address decoder 5 is connected to control bus a and address bus b, and outputs input register write signal d and output multiplexer selection read signal e.

入力レジスタ6は、入力レジスタ書き込み信号dにより
データバスCのデータを読み込み、論理演算入力fを論
理演算回路7.1〜nに出力する。
Input register 6 reads data on data bus C in response to input register write signal d, and outputs logic operation input f to logic operation circuits 7.1 to 7.n.

論理演算回路7,1〜nは論理回路で構成され、論理演
算人力fを入力し、各々の分担する論理演算、AND、
OR,NOT等を論理演算出力g、1〜nに出力する。
The logic operation circuits 7, 1 to n are composed of logic circuits, input the logic operation power f, and perform the respective logic operations, AND,
OR, NOT, etc. are output to logical operation outputs g, 1 to n.

出力マルチプレクサ8は、出力マルチプレクサ選択読み
出し信号eにより論理演算出力g、1〜nを選択し、デ
ータバスCに出力する。
The output multiplexer 8 selects the logic operation outputs g, 1 to n based on the output multiplexer selection read signal e, and outputs them to the data bus C.

第3図は第1図における汎用コンピュータ1が、論理演
算部4を制御して行う論理演算の処理フローの一例を示
す、汎用コンピュータ1は、論理演算入力を入力レジス
タに書き込み(ステップ10)、論理演算出力を結果レ
ジスタから読み出すくステップ11〉、論理演算回路7
.1〜nの濱箪速度が十分高速ならば、前記フローは汎
用コンピュータの2命令で実行される。
FIG. 3 shows an example of the processing flow of a logical operation performed by the general-purpose computer 1 in FIG. 1 by controlling the logical operation section 4. The general-purpose computer 1 writes a logical operation input to an input register (step 10), Step 11 of reading the logic operation output from the result register, logic operation circuit 7
.. If the processing speeds 1 to n are sufficiently high, the above flow can be executed by two instructions of a general-purpose computer.

〔発明の効果〕〔Effect of the invention〕

本発明の論理シミュレータは、CPUとメモリを持つ汎
用コンピュータに論理シミュレーション用論理演算部を
付加した構成により、ソフトウェアシミュレータより高
速であり、汎用コンピュータと論理演算部のハードウェ
アコストで実現できるので、ハードウェアシミュレータ
よりも安価であり、かつ、論理シミュレーシ、ヨンに使
用しない時は、汎用コンピュータとして使用できるとい
う効果がある。
The logic simulator of the present invention has a configuration in which a logic operation section for logic simulation is added to a general-purpose computer having a CPU and memory, so it is faster than a software simulator and can be realized with the hardware cost of a general-purpose computer and logic operation section. It is cheaper than a software simulator, and has the advantage that it can be used as a general-purpose computer when not used for logic simulation.

カレジスタ書き込み信号、e・・・出力マルチプレクサ
選択読み出し信号、f・・・論理演算出力、g、 1〜
n・・・論理演算出力1〜n、h・・・出力マルチプレ
クサ出力信号。
register write signal, e...output multiplexer selection read signal, f...logical operation output, g, 1~
n: Logical operation outputs 1 to n, h: Output multiplexer output signal.

Claims (1)

【特許請求の範囲】[Claims] CPUとメモリを含んで構成される汎用コンピュータと
、前記CPUからの制御により論理シミュレーション用
論理演算を実行する論理演算部とを含むことを特徴とす
る論理シミュレータ。
A logic simulator comprising: a general-purpose computer including a CPU and a memory; and a logic operation section that executes logic operations for logic simulation under control from the CPU.
JP2061357A 1990-03-12 1990-03-12 Logic simulator Pending JPH03260871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2061357A JPH03260871A (en) 1990-03-12 1990-03-12 Logic simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2061357A JPH03260871A (en) 1990-03-12 1990-03-12 Logic simulator

Publications (1)

Publication Number Publication Date
JPH03260871A true JPH03260871A (en) 1991-11-20

Family

ID=13168828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2061357A Pending JPH03260871A (en) 1990-03-12 1990-03-12 Logic simulator

Country Status (1)

Country Link
JP (1) JPH03260871A (en)

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