JPS59127445A - Memory access circuit - Google Patents

Abstract

PURPOSE:To perform optional interleaving and deinterleaving by varying only memory contents with regard to a memory access circuit which is used for a PCM reproducing device, etc. CONSTITUTION:The value of a write word counter 3-d is selected by a selector 3-g in writing operation to access addresses of memories 3-f' and 3-f''. The high- order eight bits are added to the value of a write frame counter 3-c to obtain the high-order address, and the low-order four bits are used as the low-order four-bit address as it is, so the operation of the write frame counter 3-c is performed. The value of a read word counter 3-b is selected by a selector 3-e in reading operation to access either of the memories 3-f' and 3-f''. The high-order eight bits are added to the output of a counter 3-a to obtain the high-order eight bits of a memory 3-j, and the low-order four-bit address value is equal to the value of the memory 3-f'', so the operation of the memory 3-j is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access circuit used in a PCM playback device or the like.

FIG. 1 shows an example of an interleave type used in PCM paleogetic devices and the like. In this example, the interleaving length D=16 is 16 words per frame. In FIG. 1, 1-■ indicates a write address, and 1-0 indicates a read address. Writing and reading in this example are realized using conventional hardware and are shown in FIG. In Figure 2, 2-
(4) is a read frame counter, 2-■ is a read word counter, 2-■ is a write frame counter,
2-■ is a write word counter, 2-■ is an arithmetic unit that realizes D=16, 2- is a selector, 2-@ is a RAM,
2-■ is a controller. During writing, the counter values of the fill frame counter 2-■ and write word counter 2-■ are selected by the selector 2-■ in response to a select signal from the controller 2-■, and are stored in the RAM 2-■.
Determine the @ address. At the time of reading, a predetermined address is generated by subtracting the counter value of the read frame counter 2-■ and the counter value of the read word counter 2-■.
2-(m). In this example, D-
16, this is done every time the read word counter value is subtracted from the read frame counter value. In other words, if the l-th word read frame position is 14 and the word number is m (o<m<, 7), the read frame n is n==n1-16Xm, and the address of (n, m) can be accessed. K becomes.

When implementing the interleaving method in hardware using the conventional method, for example, interleaving is performed at the write address of wIJ1 Figure 1-■ and the read end address of 1-@, an adder is required to implement l-■. In addition, it is necessary to change the control section, etc. in order to realize l-〇.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access circuit that enables arbitrary interleaving and dinterleaving by simply changing the contents of a ROM.

An embodiment of the present invention will be described below with reference to FIG.

3-■ is a read frame counter, 3-■ is a read word counter, 3-■ is a write frame counter,
3-■ is a write word counter, 3-■ is a word counter selector, 3-■ and 3-GD are storage elements (for example, ROM ),
3-@ is a selector that selects the read/write frame counter value, 3-■ is an adder or subtractor (adder in this example), 3-■ is a control circuit, and 3-■ is a RAM. Here, 3 In the case of FIG. 1, the ROMs -(f) and 3-(f) may be configured to have a capacity of 16×2=32 words and 12 bits/word. In addition, the data to be stored in this ROM is not shown in Table 1 in the case of l-■, l-@ in Figure 1 (first method), and is data l-■, l in Figure 1.
In the case of −■ (second method), the data is shown in Table 2.

The circuit operation of FIG. 3 is exactly the same in both the first method and the second method. Therefore, the circuit operation will be explained in the second method. First, during writing, the write word counter value is selected by selector 3-■, and ROM3-[F],
3-C) address Table 1 Table 2 Access 1-1 For example, if the counter value is DA, it is 1 (HE
X) is output from ROM3-■, 3-■, upper 8bit
t is added to the value of the frame counter 3-■,
The addition result NlN2 + DI = NlN2 becomes the upper address of the memory. Further, the lower 4 bits become the lower 4 bit address of the memory as they are, the output of the result ① becomes door 11, the memory address is NlNz0OL becomes the upper address, and the lower address is 1. By the above operation, the write frame counter l--2 in FIG. 3 can be operated.

Also, when reading, the value of the read word counter 3-b is selected by the selector 3-■ and the ROM 3-■, 3-
■Access one of the following.

At this time, it is assumed that the other 6M address line output from the control circuit 3-2 is +)l'L.

As a result, the addresses of ROM3-■ and 3-■ are 8 to 15.
will be accessed, and the corresponding relative address data will be accessed at the time of reading. For example, if the output of the read word counter 3-■ is 61'', the upper 8 bits output F〆, and the lower 4 bits output 61''. The upper 8 bits are added to the output of the read frame counter 3-■, and EF is added to the output of the read frame counter 3-■.
It becomes the upper 8-bit address of RAM3-■. The lower 4 bit address value becomes the value 3-O. If we consider the above, we can perform the RAM operation shown in Figure 1, 1-0.

As another example, a case having an interleaved structure shown in FIG. 4 will be described. 4-■ is for filling in, 4-■ is for C1 reading, 4-■ is for C2 reading, 4-■ is for D/A.
Read. The reading order of the D/A is as shown by the numbers in FIG. The hardware configuration that realizes this case is shown in Figure 3.
The contents of O are added and shown by broken lines of 3-[present] which are output to the ROM address control lines (from control circuit 3-■ to ROM3-O, 3-e) corresponding to each state. ) just add %s.

In this case, the operation table for 4-■, 4-■, 4-■
3 is accessed within l frame. The contents of the first ROM for realizing the access shown in FIG. 4 are shown in Table 3. In this example, the upper G bit is data for addition as write data, or data for subtraction as data for C2 and D/A, that is, data converted into a two's complement value of the subtraction value in the ROM. (the first step in which addition and subtraction are performed by the adder).

As stated above, various memory access methods can be used by simply changing the ROM contents without requiring any major changes to the hardware.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a memory access method, Fig. 2 is a block diagram showing a conventional column, Fig. 3 is a block diagram showing an embodiment of the present invention, and the fourth figure is a block diagram showing a column used for other purposes according to the present invention. FIG. 3-■...Reading frame counter, 3-■...
Read word counter, 3-■...Start frame counter, 3-■...Write word counter. 3-■・-・R(JM, 3-■・・・・1(σM, 3-[
Yes]...'110 calculator, 3-■...RAM, 3-■
...Control circuit. Patent applicant Akai Electric Co., Ltd.

Claims (1)

[Claims] In an interleave/dinterleave circuit using memory elements that converts burst errors into random errors in a transmission line that causes burst errors, the address of the access memory element is read out and the frame counter and the write frame counter are , a storage element having a frame address and a mutual value of the address to be accessed, an adder or subtracter for adding or subtracting the data of the storage element and the counter value, and a control circuit for controlling the component. A memory access circuit characterized by comprising: