JPS59149062A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59149062A JPS59149062A JP58022744A JP2274483A JPS59149062A JP S59149062 A JPS59149062 A JP S59149062A JP 58022744 A JP58022744 A JP 58022744A JP 2274483 A JP2274483 A JP 2274483A JP S59149062 A JPS59149062 A JP S59149062A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- layer
- schottky
- ions
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路の製造方法に係り、特にその要
素としてのショットキバリアダイオードを形成する製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a Schottky barrier diode as an element thereof.
半導体集積回路に含まれるショットキバリアダイオード
は、特にショットキゲートＦＥＴ（電界効果ｌ・ランジ
スタ）金主な能動素子として持つＧａＡｓ等の化合物半
導体集積Ｎ路においては、従来ケート金属を用いて形成
されていた。そのため第１図のように半導体基板１にゲ
ート金属３をマスクとしてｎ９イオン５をイオン打込み
を行なうセルフアラインメント形の素子においては、高
濃度ｎ＋層４をダイオードとして兼ねることができず、
大きな接合容量を持ったダイオードが必要な時等には新
たにそのためのイオン打込みを行なう必要があった。Schottky barrier diodes included in semiconductor integrated circuits, particularly in Schottky gate FETs (field effect transistors), have traditionally been formed using gate metals, especially in compound semiconductor integrated circuits such as GaAs that have gold as the main active element. . Therefore, in a self-alignment type device in which n9 ions 5 are implanted into a semiconductor substrate 1 using the gate metal 3 as a mask as shown in FIG. 1, the high concentration n+ layer 4 cannot double as a diode.
When a diode with a large junction capacitance is required, it is necessary to perform additional ion implantation.
なお、図において２はｎ型活性層である。Note that in the figure, 2 is an n-type active layer.
本発明の目的は、ＦＥＴの能動層よシ高濃度の層にショ
ットキバリアダイオードを形成し、しかもそのイオン打
込みをオーミック接触用のｎ＋層打込みと兼ねる方法を
提供することにある。An object of the present invention is to provide a method for forming a Schottky barrier diode in a layer higher in concentration than the active layer of an FET, and also for implanting ions into the n+ layer for ohmic contact.
第１図に示すセルフアラインメント形の素子を持つ集積
回路では、大きな接合容量を持つダイオードを作る場合
にもゲート電極の下にｎ＋イオン打込みを行なうことが
できない。そこで第二層の配線金属を層間絶縁膜に開け
た穴（コンタクトホール）を介してｎ９イオン打込みを
行なった半導体に直接接触させてショットキダイオード
を形成することにより大容量のダイオードを得る。In the integrated circuit having the self-alignment type element shown in FIG. 1, it is not possible to implant n+ ions under the gate electrode even when making a diode with a large junction capacitance. Therefore, a large capacitance diode is obtained by directly contacting the second layer wiring metal with the semiconductor into which n9 ions have been implanted through a hole (contact hole) made in the interlayer insulating film to form a Schottky diode.
以下、本発明の一実施例を第２図によシ説明する。まず
半絶縁性ＧａＡＳ基板結晶１中の集積回路の能動層部分
となる領域に、イオン打込み法によりチャネルを形成す
る。第２図（ａ）はその様子を示したもので、例えば半
絶縁性ＧａＡｓ基板１を、適当な表面処理を施した後、
通常のホ） ＩＪソゲラフイエ程によシイオン打込みさ
れる部分のみに開口部を持つマスク６を形成する。この
場合、打ち込む不純物はＳｉ＋であり、ｎ型チャネル層
２０打込みエネルギーは７５ｋｅ■、ドーズ量は２×１
０”ｃｒｎ−”である。次にゲート電極３として高耐熱
電極であるタングステンあるいはチタンタングステンを
スパッタ法あるいは電子ビーム蒸着法で被層する。そし
てこのゲート電極３をマスクとしてｎ０層１０のイオン
打込み（５）ヲ行ないセルフアライメント型のＦＥＴ’
！ｉ形成する。この時第２図（ａ）の左に示すようにダ
イオード部にも高濃度イオン打込みを行い、大容量のシ
ョットキダイオードの活性層４とする。打込みイオンは
Ｓｉで打込みエネルギーは１５０ ｋ ｅ Ｖ、 ド
ーズ量ｌＸ１０ｔｓｃｒｒ１−２である。ＣＶＤ５ｉ０
２を保護膜とした８０００２０分間のアニールの後同図
（ｂ）に示すようにオーミック電極７の形成を行なう。An embodiment of the present invention will be explained below with reference to FIG. First, a channel is formed by ion implantation in a region of the semi-insulating GaAS substrate crystal 1 that will become the active layer portion of the integrated circuit. FIG. 2(a) shows the situation. For example, after a semi-insulating GaAs substrate 1 is subjected to an appropriate surface treatment,
Normal E) A mask 6 is formed which has openings only in the portions to be implanted with silicon ions during the IJ sogerhead process. In this case, the impurity to be implanted is Si+, the implantation energy for the n-type channel layer 20 is 75ke, and the dose is 2×1.
0"crn-". Next, tungsten or titanium tungsten, which is a highly heat-resistant electrode, is coated as a gate electrode 3 by sputtering or electron beam evaporation. Then, using this gate electrode 3 as a mask, ion implantation (5) of the n0 layer 10 is performed to form a self-alignment type FET'.
! i form. At this time, as shown on the left side of FIG. 2(a), high-concentration ion implantation is also performed in the diode portion to form the active layer 4 of a large-capacity Schottky diode. The implanted ions were Si, the implantation energy was 150 keV, and the dose was 1×10tscrr1-2. CVD5i0
After annealing for 800020 minutes using No. 2 as a protective film, an ohmic electrode 7 is formed as shown in FIG.
オーミック電極にはＡ ｕ Ｇ ｅ ／ Ｎ Ｉ ／
Ａ ｕの三層構造を真空蒸着し、４００Ｃ３分間アロ
イを行なって形成する。Ohmic electrodes include A u G e / N I /
A three-layer structure of Au is vacuum deposited and alloyed with 400C for 3 minutes.
図に示すようにＦＥＴのソース、ドレイン部α〔および
ショットキダイオードのオーミック電極７にリフトオフ
法によってパターンニングを行なう。As shown in the figure, the source and drain portions α of the FET and the ohmic electrode 7 of the Schottky diode are patterned by the lift-off method.
次いでリン濃度５モル％のＰ２Ｏ（ＩＪン含有ガラス）
膜をＣＶＤ法によって全面に被着し層間絶縁膜８とする
。（第２図（Ｃ）。）この絶縁膜にダイオードのショッ
トキ電極を含む必要な部分に穴明けを行ない、ＭＯＺＡ
ｕを蒸着してＡｒイオンミリングでパターンニングを行
なうことによシ最後の第２層配線９を形成する。この配
線９は集積回路の中の各素子の電気的接続を行なうと共
に、ショットキダイオードのショットキ１Ｍ、ａともな
っている。この点が本発明において重要な点である。第
２図（ｄ）は児成した集積回路の断面図である。Next, P2O with a phosphorus concentration of 5 mol% (IJ-containing glass)
A film is deposited over the entire surface by CVD to form an interlayer insulating film 8. (Figure 2 (C).) Holes are made in this insulating film at the necessary parts including the Schottky electrode of the diode, and the MOZA
The final second layer wiring 9 is formed by depositing u and patterning by Ar ion milling. This wiring 9 electrically connects each element in the integrated circuit, and also serves as a Schottky diode 1M, a. This point is important in the present invention. FIG. 2(d) is a cross-sectional view of the formed integrated circuit.
本発明によれば、従来の方法ではＦＥＴの活性層と同じ
キャリア濃度でなければ形成できなかったショットキダ
イオードのキャリア濃度を高くすることができ、大容量
のダイオードを得ることができる。また、従来の方法で
はダイオードのキャリア濃度を最適化するためには、工
程を増やしてそのためのイオン打込みを行う必要があっ
たが本発明の方法によれば、ｎ＋イオン打込みの条件を
適当に選べば、少い工程で最適なキャリア濃度のダイオ
ードを得られ、優れた性能を実現することができる。例
えば、容量結合を用いた集積回路では大容量を必要とし
、集積化を図る上で、チップ面積が大きくなる。本発明
の製造方法でダイオ−ドラ製作すると約ダイオード面棟
が１／３になシ、容量結合型回路を用いた集積回路は高
集積化を可能にした。According to the present invention, it is possible to increase the carrier concentration of a Schottky diode, which could not be formed with the conventional method unless the carrier concentration is the same as that of the active layer of an FET, and it is possible to obtain a diode with a large capacity. In addition, in the conventional method, in order to optimize the carrier concentration of the diode, it was necessary to increase the number of steps and perform ion implantation for that purpose, but according to the method of the present invention, the conditions for n+ ion implantation can be appropriately selected. For example, a diode with an optimal carrier concentration can be obtained with fewer steps, and excellent performance can be achieved. For example, an integrated circuit using capacitive coupling requires a large capacity, which increases the chip area for integration. When a diode is manufactured using the manufacturing method of the present invention, the surface area of the diode is reduced to about 1/3, and an integrated circuit using a capacitively coupled circuit can be highly integrated.
第１図はセルフアラインメント型Ｆ’ＥＴの００イオン
打込み工程を示す断面図、Ｗ、２図は本発明の集積回路
のプロセスを示す断面図である。
１・・・半絶縁性ＧａＡｓ基板結晶、２・・・ｎ型活性
層、３・・・ゲート電極、４・・・高濃度ｎ９層、５・
・・Ｓｉイオンビーム、６・・・ホトレジスト、７・・
・オーミック電極、８・・・層間絶縁膜、９・・・配線
金属。
代理人 弁理士 高橋明夫FIG. 1 is a sectional view showing the 00 ion implantation process of a self-alignment type F'ET, and FIG. 2 is a sectional view showing the process of an integrated circuit according to the present invention. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate crystal, 2... N-type active layer, 3... Gate electrode, 4... High concentration n9 layer, 5...
...Si ion beam, 6...photoresist, 7...
- Ohmic electrode, 8... interlayer insulating film, 9... wiring metal. Agent Patent Attorney Akio Takahashi
Claims (1)
第二層の配線金属をショットキ・メタルに用いて形成す
ることを特徴とする半導体装置の製造方法。When manufacturing a semiconductor integrated circuit with two-layer wiring,
A method of manufacturing a semiconductor device, characterized in that a second layer of wiring metal is formed using Schottky metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58022744A JPS59149062A (en) | 1983-02-16 | 1983-02-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58022744A JPS59149062A (en) | 1983-02-16 | 1983-02-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59149062A true JPS59149062A (en) | 1984-08-25 |
| JPH0434830B2 JPH0434830B2 (en) | 1992-06-09 |
Family
ID=12091207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58022744A Granted JPS59149062A (en) | 1983-02-16 | 1983-02-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149062A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6081859A (en) * | 1983-10-11 | 1985-05-09 | Matsushita Electric Ind Co Ltd | Schottky barrier semiconductor device |
-
1983
- 1983-02-16 JP JP58022744A patent/JPS59149062A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6081859A (en) * | 1983-10-11 | 1985-05-09 | Matsushita Electric Ind Co Ltd | Schottky barrier semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0434830B2 (en) | 1992-06-09 |
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