JPS59155143A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59155143A JPS59155143A JP58028817A JP2881783A JPS59155143A JP S59155143 A JPS59155143 A JP S59155143A JP 58028817 A JP58028817 A JP 58028817A JP 2881783 A JP2881783 A JP 2881783A JP S59155143 A JPS59155143 A JP S59155143A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alumina
- etching
- substrate
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Landscapes
- Element Separation (AREA)
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、酸化アルミニウム(以下、アルミナと称す)
を用いて電極間および素子間を電気的に分離するアルミ
ナ膜分離法に関するものである。[Detailed Description of the Invention] The present invention provides aluminum oxide (hereinafter referred to as alumina)
The present invention relates to an alumina membrane separation method that electrically isolates between electrodes and between elements.
例えば、第1図に示すように、従来よシ行われているo
aAsVwットキ障壁ゲー)FETの電気的素子分離は
、能動層3以外の領域を電気的絶縁層であるバッファ層
2に、ある程度入る深さまでエツチングしてメサ構造に
し、ゲート4.ソース5およびドレイン6それぞれの電
極をメタライズして能動層3表面からメサエッチング領
域まで配線を引き出す方法が採られている。しかしなが
ら、この方法によると電極配線の厚さが0.5〜0.8
μmに対し、メサエッチング深さが1,0μm以上であ
ることから、メサ段差部7で電極配線の断線が生じ易い
欠点がある。For example, as shown in FIG.
Electrical element isolation of the FET is achieved by etching the area other than the active layer 3 into the buffer layer 2, which is an electrically insulating layer, to a certain depth to form a mesa structure, and forming a gate 4. A method is adopted in which the electrodes of the source 5 and drain 6 are metalized and wiring is drawn from the surface of the active layer 3 to the mesa etched region. However, according to this method, the thickness of the electrode wiring is 0.5 to 0.8
Since the mesa etching depth is 1.0 μm or more compared to 1.0 μm, there is a drawback that the electrode wiring is easily disconnected at the mesa step portion 7.
そこで、エツチングによる段差を防止するために、エツ
チングしたところを誘電体で埋めることが行なわれてい
る。誘電体としては、通常、酸化シリコンや有機物が使
用されるが、それらの耐熱性や形成方法の問題を解決す
るためにアルミナを使用することが提案されている。Therefore, in order to prevent the step difference caused by etching, the etched area is filled with a dielectric material. Silicon oxide and organic materials are normally used as dielectrics, but the use of alumina has been proposed to solve problems with their heat resistance and formation methods.
すなわち、選択的にエツチングした箇所を含めて基板全
面にアルミニウム層を形成し、エツチング部分を埋める
アルミニウム層を選択的にアルミす層Kかえて残りを除
去するか、又は全面アルミニウム層をアルミナ層に変換
して選択的にエツチング除去するものであった。しかし
ながら、この方法は少なくともエツチング用マスクを除
去する工程、アルミニウム層を形成する工程、アルミナ
層に変換する工程、および選択的にアルミナ層又はアル
ミニウム層を除去する工程が必要である。In other words, an aluminum layer is formed on the entire surface of the substrate including the selectively etched areas, and the aluminum layer filling the etched areas is selectively aluminized and the rest is removed, or the entire aluminum layer is replaced with an alumina layer. It was converted and selectively removed by etching. However, this method requires at least the steps of removing the etching mask, forming the aluminum layer, converting it to an alumina layer, and selectively removing the alumina layer or the aluminum layer.
つまシ、製造工程が長くなってしまう。Unfortunately, the manufacturing process becomes longer.
本発明は、工程が簡単なアルミナ膜分離法を提供するこ
とを目的とする。An object of the present invention is to provide an alumina membrane separation method with simple steps.
本発明は、耐エツチング膜をマスクとして選択的に基板
をエツチングし、全面にアルミナ層を直接設け、耐エツ
チング膜およびこの上のアルミナ膜をリフトオフ法で同
時に除去することを特徴とする。The present invention is characterized in that the substrate is selectively etched using the etching-resistant film as a mask, an alumina layer is directly provided on the entire surface, and the etching-resistant film and the alumina film thereon are simultaneously removed by a lift-off method.
以下、本発明を図面によシ説明する。The present invention will be explained below with reference to the drawings.
第2図は、本発明の一実施例であるG a A s V
1ットキ障壁ゲー) F E T、の製造工程における
断面図である。FIG. 2 shows a G a A s V which is an embodiment of the present invention.
FIG. 1 is a cross-sectional view in the manufacturing process of a one-piece barrier game.
先ず、第2図(a)に示すように、(100)面を主面
とする半絶縁性GaAs基板1に1013〜1014c
WL−3のキャリア濃度をもつバッファ層2を3〜7μ
m1その上に0.5〜1.5X10”儒−3のキャリア
濃度をもつn型能動層3を0.5〜0.9μm連続的に
エピタキシャル成長する。First, as shown in FIG. 2(a), a semi-insulating GaAs substrate 1 having a (100) plane as a main surface is coated with 1013 to 1014 c.
Buffer layer 2 with a carrier concentration of WL-3 is 3 to 7μ
On the m1 layer, an n-type active layer 3 having a carrier concentration of 0.5 to 1.5×10”f−3 is epitaxially grown continuously to a thickness of 0.5 to 0.9 μm.
次に、第2図(b)に示すように、フォトレジスト8を
塗布し、通常のりソグラフィ技術で素子動作領域をパタ
ーニングして絶縁分離領域となる基板面になるようにパ
ターニングする。Next, as shown in FIG. 2(b), a photoresist 8 is applied, and the device operating area is patterned using ordinary lithography technology to form a substrate surface that will become an insulating isolation area.
次に、第2図1c)に示すように1例えば硫酸H!S0
4と過酸化水素水H20!混合液で、バッファ層2にお
よそ2000〜3000A入シ込むまで基板表面10か
らエツチングする。Next, as shown in FIG. 2 1c), 1, for example, sulfuric acid H! S0
4 and hydrogen peroxide H20! The mixed solution is etched from the substrate surface 10 until approximately 2000 to 3000 A is injected into the buffer layer 2.
しかる後、第2図(diに示すようにスパッタリング法
によシアルミナをエツチング深さと等しい厚さになるよ
うに全面に付着させる。このとき、フォトレジスト8の
側面にはアルミナ膜は形成されない。そして、第2図(
e)に示すよ゛うに、素子動作領域上の7オトレジスト
8およびその上のアルミナ層9′を有機溶剤によシ取り
除く、つま少リフトオフしする。す7トオ7ができるの
は、フォトレジスト8の側面が霧出しているかである。Thereafter, as shown in FIG. 2 (di), sialumina is deposited on the entire surface by sputtering to a thickness equal to the etching depth. At this time, no alumina film is formed on the side surfaces of the photoresist 8. , Figure 2 (
As shown in e), the photoresist 8 on the device operating area and the alumina layer 9' thereon are removed using an organic solvent, and a slight lift-off is performed. 7 is formed when the sides of the photoresist 8 are misted out.
次に、アルミナ層9とバッフ7層2との密着性を増すた
めに、図示しない100〜400℃の水素H!ガスるる
いは不活性ガス(Ar、N2)雰囲気下で熱処理を施す
。このあと、第2図ば)に示すように従来から実施され
ている方法でゲート4.ソース5゜ドレイン6の電極形
成を行い、各々の電極をアルミナ層9の上に引き出し電
極パッドを形成する。Next, in order to increase the adhesion between the alumina layer 9 and the buff 7 layer 2, hydrogen H! Heat treatment is performed under a gas atmosphere or an inert gas (Ar, N2) atmosphere. After this, as shown in FIG. 2, gate 4. Source 5° and drain 6 electrodes are formed, and each electrode is drawn out onto the alumina layer 9 to form an electrode pad.
上記の製造方法によれば、アルミナ層表面と能動層表面
とが同一高さにあることから素子表面上が平担化され、
従って電極配線の断線は起こらない。しかも、アルミナ
層を直接形成し、かつリフトオフ法で不要なアルミナ層
を除去できるので。According to the above manufacturing method, since the surface of the alumina layer and the surface of the active layer are at the same height, the surface of the element is flattened.
Therefore, disconnection of the electrode wiring does not occur. Moreover, the alumina layer can be directly formed and unnecessary alumina layers can be removed using the lift-off method.
工程も簡略化される。The process is also simplified.
以上、詳細に説明したように、本発明によnば能動層周
囲にアルミナ層を設けることによシ、電極配線の断線を
防止できるとともに電気絶縁性の高いことから各電極間
および能動層と電極パッド間の電気絶縁分離が可能とな
)安定した特性を得る効果がある。As explained above in detail, according to the present invention, by providing an alumina layer around the active layer, it is possible to prevent disconnection of electrode wiring and to provide high electrical insulation between each electrode and the active layer. This has the effect of obtaining stable characteristics (enabling electrical insulation separation between electrode pads).
尚、本発明は、ディスクリートのみならずIC−の素子
間絶縁分離にも適用でき、また基板素材としてはStな
ど他の半導体材料も可能である。It should be noted that the present invention can be applied not only to discrete devices but also to insulation isolation between IC- elements, and other semiconductor materials such as St can be used as the substrate material.
第1図は従来の半導体装置の断面図、第2図(at乃至
(f)は本発明の一実施例による製造方法を工程贋に示
した断面図である。
1・・・・・・半絶縁性GaAs基板、2・・・・・・
バッファ層、3・・・・・・n型能動層、4・・・・・
・ゲート、5・・・・・・ソース、6・・・・・・ドレ
イン、7・・・・・・メサ段差部、8・・・・・・フォ
トレジスト、9・・・・・・アルミナ、10・・・・・
・基板表面。FIG. 1 is a cross-sectional view of a conventional semiconductor device, and FIG. 2 (at to (f)) are cross-sectional views showing a manufacturing method according to an embodiment of the present invention. Insulating GaAs substrate, 2...
Buffer layer, 3...N-type active layer, 4...
・Gate, 5... Source, 6... Drain, 7... Mesa step, 8... Photoresist, 9... Alumina , 10...
・Substrate surface.
Claims (1)
スクを形成する工程と、該耐エツチング性マスクを用い
て半導体基板を選択的にエツチングする工程と、全面に
酸化アルミニウム層を形成する工程と、前記耐エツチン
グ性マスクおよび耐エツチング性マスク上の酸化アルミ
ニウム層を同時に除去する工程とを備えたことを特徴と
する半導体装置の製造方法。selectively forming an etching-resistant mask in an element formation region of a semiconductor substrate; selectively etching the semiconductor substrate using the etching-resistant mask; forming an aluminum oxide layer over the entire surface; A method for manufacturing a semiconductor device, comprising the step of simultaneously removing the etching-resistant mask and the aluminum oxide layer on the etching-resistant mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58028817A JPS59155143A (en) | 1983-02-23 | 1983-02-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58028817A JPS59155143A (en) | 1983-02-23 | 1983-02-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59155143A true JPS59155143A (en) | 1984-09-04 |
Family
ID=12258953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58028817A Pending JPS59155143A (en) | 1983-02-23 | 1983-02-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155143A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014090190A (en) * | 2006-03-14 | 2014-05-15 | Northrop Grumman Systems Corp | LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE |
-
1983
- 1983-02-23 JP JP58028817A patent/JPS59155143A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014090190A (en) * | 2006-03-14 | 2014-05-15 | Northrop Grumman Systems Corp | LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE |
| JP2016213478A (en) * | 2006-03-14 | 2016-12-15 | ノースロップ グラマン システムズ コーポレーション | Leak barrier for GaN-based HEMT active devices |
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