JPS5918657A - 集積回路用基板の製造方法 - Google Patents
集積回路用基板の製造方法Info
- Publication number
- JPS5918657A JPS5918657A JP57127227A JP12722782A JPS5918657A JP S5918657 A JPS5918657 A JP S5918657A JP 57127227 A JP57127227 A JP 57127227A JP 12722782 A JP12722782 A JP 12722782A JP S5918657 A JPS5918657 A JP S5918657A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- nitride film
- single crystal
- porous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Landscapes
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127227A JPS5918657A (ja) | 1982-07-21 | 1982-07-21 | 集積回路用基板の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127227A JPS5918657A (ja) | 1982-07-21 | 1982-07-21 | 集積回路用基板の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5918657A true JPS5918657A (ja) | 1984-01-31 |
| JPS6249733B2 JPS6249733B2 (2) | 1987-10-21 |
Family
ID=14954873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57127227A Granted JPS5918657A (ja) | 1982-07-21 | 1982-07-21 | 集積回路用基板の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5918657A (2) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5439843A (en) * | 1992-01-31 | 1995-08-08 | Canon Kabushiki Kaisha | Method for preparing a semiconductor substrate using porous silicon |
-
1982
- 1982-07-21 JP JP57127227A patent/JPS5918657A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5439843A (en) * | 1992-01-31 | 1995-08-08 | Canon Kabushiki Kaisha | Method for preparing a semiconductor substrate using porous silicon |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6249733B2 (2) | 1987-10-21 |
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