JPS59200469A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve the reduction of the resistance of the source and drain regions and the gate electrode with good reproducibility by adhering of a metallic film by making an insulating film left on the side wall of the gate electrode to be made into a thermal oxide film. CONSTITUTION:A field oxide film 22 and a gate oxide film 23 are formed on the P type Si substrate 21 and a polycrystalline Si film 24 including phosphorus and an Si3N4 film 25 are then deposited followed by etching to form a gate electrode pattern. After that, a thermal oxide film 26 is formed by wet oxidation followed by etching to leave the thermal oxide film 26 only on the side wall of the polycrystalline Si film 24. After that, As is ion-implanted to form N type layers 27 and 28 to become the source and drain regions and W-films 291-293 are selectively coated which are covered with an SiO2 film 30 to form Al wiring 311 and 312. As the thermal oxide film has good controllability of film thickness, the insulating properties between the gate and the source and drain can be set within the desired range surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device having a polycrystalline silicon gate structure.

[Technical background of the invention and its problems]

In semiconductor integrated circuits, as the degree of integration increases, it is desired that the manufacturing process temperature be lowered. Especially in MO8 type semiconductor devices,
When the dart length is about lpm or less, a high-temperature thermal process of 900 to 1000° C. after forming the source and drain regions significantly multiplies the short channel non-effect, resulting in characteristic deterioration.

On the other hand, when forming source and drain regions by ion implantation, heat treatment at 800° C. or lower is not sufficient to activate the implanted impurities. Therefore, if an MO8 type semiconductor device is manufactured using a process at such a low temperature, a problem arises in that the resistance of the source and drain regions becomes high.

As a method to solve such problems, there is a method of gluing a metal film on the source and drain regions to lower their resistance. Examples thereof will be explained with reference to FIGS. 1a) to (d)K. A finoside oxide film 12 is formed on a P-type Si substrate 11, and a polycrystalline St.
A dirt electrode 14 is formed, and an n-type impurity is ion-implanted to form a shallow n-type diffusion layer 15 in the source and drain regions. .

Form 16K (,). Next, a SiO film 17 is deposited on the entire surface by CVD (b). After that, the entire surface is etched by reactive ion etching (RIB), and CVD5 is selectively etched only on the side wall of the dart electrode 14.
iO, leaving the film 17 (C).

Next, RI on the source and drain regions is rinsed with dilute hydrofluoric acid.
After removing the region damaged by E, n-type impurity ions are again implanted to form the male-type diffusion layer 15. which is deeper than the n-type diffusion layer 158, 16□. .

16, forming (d). After this, the metal film 19□~ is self-aligned over the source and drain regions and the dirt electrode.
19. (e). This metal film 191-19
．． As a formation method, for example, a method of depositing PT on the entire surface and performing heat treatment to selectively form a PT silicide film only on silicon and removing the unreacted PT film, or WF,
.

There is a method of selectively growing a W, Mo film only on silicon by a CVD method using M61F.

After this, although not shown, the entire surface is CVed according to the usual method.
Cover with a D5iO film and open contact holes to form wiring.

As a result, even if impurity activation in the source and drain regions is insufficient, the resistance of the source and drain regions can be lowered by the metal film bonded thereon.

However, this conventional method has the following drawbacks. CVD5iO deposited in the step of FIG. 1(b).

The film 17 has large in-plane thickness variations, large thickness changes at the side wall of the dirt electrode due to the stepped shape, and poor controllability of etching with dilute hydrofluoric acid. For this reason, as shown in Fig. 1(C), there is a large variation in the thickness of the CVD5iO film left on the side wall of the dirt electrode, and the CVD5iO film is retreated by dilute hydrofluoric acid rinsing before the metal film is bonded. This may cause the film to go through, or the insulation between the dirt and the source or drain may deteriorate. Also, CVD5
40□ Due to poor film thickness controllability, if ion implantation into the source and drain regions is performed only once, dirt may be offset depending on the degree of impurity re-diffusion during the ion implantation process and subsequent thermal process. The result is that the source and drain regions become deep under the gate electrode. In order to avoid this, a two-step ion implantation process is required as described above.

[Purpose of the invention]

The present invention solves the above-mentioned problems and provides a method for manufacturing a semiconductor device that can achieve low resistance with good reproducibility by gluing metal films on source, drain regions, and dirt electrodes.

[Summary of the invention]

In the present invention, a laminated film of a polycrystalline silicon film and an oxidation-resistant film, which will become a dirt electrode, is first formed on a substrate on which a dirt insulating film is formed. Then, this laminated film is turned by quarter to form a dirt electrode, and then thermal oxidation is performed to form a thermal oxide film on the source and drain regions and on the sidewalls of the ff-) electrode. Next, the thermal oxide film on the source and drain regions and the oxidation-resistant film on the dirt electrode are removed by anisotropic dry etching such as RIP, and the thermal oxide film is left on the side wall of the dirt electrode in a self-aligned manner.

After forming the source and drain regions by ion implantation, rinsing with dilute hydrofluoric acid is performed as necessary, and a metal film is plated on these regions in a self-aligned manner.

Note that the ion implantation process into the source and drain regions may be performed before the formation of a thermal oxide film or with the source and drain regions covered with a thermal oxide film. may be performed at the same time as polycrystalline silicon film deposition, or may be performed afterward.

〔Effect of the invention〕

According to the present invention, since the insulating film left on the side wall of the r-) electrode is a thermal oxide film, the controllability of the film thickness is superior to that of the conventional method using a CVDSiO2 film, and it is also resistant to uniform etching using dilute hydrofluoric acid, etc. On the other hand, the controllability is good, and the film thickness can be adjusted to 10
It can be set to 00λ or less with good reproducibility. Therefore, when a metal film is pasted onto the source and drain regions, defects such as the metal film penetrating through the source and drain regions do not occur, and the insulation between the dirt and the source and drain is ensured within the desired range. Can be set. Furthermore, since the thickness of the thermal oxide film left on the side wall of the dirt electrode is excellently controlled, the ion implantation process into the source and drain regions can be performed only once, which simplifies the process.

[Embodiments of the invention]

The manufacturing process of one embodiment of the present invention will be explained using FIGS. 2(a) to 2(f). After forming a one-field oxide film 22 of approximately 700 OA on a P-type St substrate 21, a 100-layer dirt oxide film 23 is formed in a dry oxygen atmosphere at 900° C., and then a polycrystalline silicon film 24 containing phosphorus is formed by low-pressure CVD. 3000A was deposited by the method, and then 81.A was deposited as an oxidation-resistant film.
About 500 N4 films 25 are deposited by the same low pressure CVN method (Otori). After this, a resist pattern is formed and Si3
The laminated film of the N4 film 25 and the polycrystalline silicon film 24 is etched by RIB to form a gate electrode pattern (b). He conducted wet oxidation at 900℃ for 20 minutes.
A thermal oxide film 26 is formed on the source and drain regions and on the sidewalls of the polycrystalline silicon film 24 (c). And H2 and CF
The Si, N4 film 25 and the thermal oxide film 26 on the source and drain regions are etched and removed by RIE using
The thermal oxide film 26 is left only on the sidewalls of the polycrystalline silicon film 24. After this, is the fluorine carbon compound deposited on the silicon? Remove the rimmer with oxygen plasma etching,
Furthermore, the exposed silicon surface is approximately 200-300λ, CF
, and 02 by plasma etching, the As was removed by plasma etching using a mixed gas of 5
Ions are implanted and heat treatment is performed at 800° C. for 30 minutes in diluted oxygen to form n-type layers 27 and 28 that will become source and drain regions (d). After cooking, rinse the sauce with dilute hydrofluoric acid.
The thin oxide film on the drain region and the dirt electrode is removed, and approximately 400% of
ACIWII291-29. selectively deposit (e)
. Finally, the entire surface is covered with CVD5iO film 30, contact holes are formed, and AJ wiring 311.31! By forming this, an MO8 type semiconductor device is completed (f).

According to this embodiment, the channel length can be easily controlled, and the channel length is 1 μm.
We were able to realize a MOS FET with a channel length of m with good reproducibility. In addition, the dart withstand voltage has been significantly improved, and compared to the conventional method explained in Fig. M1, it is 8 M V/C.
It was confirmed that failure modes of less than 11 were reduced by about 20%.

As described above, according to the present invention, it is possible to realize an MO8 type semiconductor device with a polycrystalline silicon gate structure in which resistance is lowered by bonding a metal film in the source and drain regions with good reproducibility and in a simple process. The dirt pressure resistance is also significantly improved.

Note that although the n-channel MO8 has been described in the embodiment, the present invention can be similarly applied to the P-channel MO8. In this case, the source and drain regions can be obtained by, for example, ion-implanting boron and performing heat treatment at about 700°C, thereby suppressing boron re-diffusion and making it possible to control (set) the channel length. The metal film can be bonded onto the drain region by the CVD method using MoF6, or by depositing a metal film such as Pi on the entire surface, forming metal silicide only on the source and drain regions, and removing unreacted metal. You may also use the method.

[Brief explanation of the drawing]

Figures 1 (c) to (d) are diagrams showing the manufacturing process of a conventional MO8 type semiconductor device, and Figures 2 (a) to (f) are diagrams showing the manufacturing process of an MO8 type semiconductor device according to an embodiment of the present invention. FIG. 21... P type 8i substrate, 22... Field oxide film, 23... Dirt oxide film, 24... Polycrystalline silicon film (dart electrode), 25... St, N, film (oxidation resistant 26... thermal oxide film, 27.28... n-type layer (
Source, drain region, 291-29. ...W film (metal film), 30...CVD5iO, film, 311.31.
...i' wiring. Applicant's agent Patent attorney Takehiko

Claims (1)

[Claims] Polycrystalline silicon film on semiconductor substrate via dirt insulating film,
Subsequently, there is a step of sequentially laminating oxidation-resistant films, a step of patterning the obtained laminated film of the oxidation-resistant film and polycrystalline silicon film to form f-) electrodes, and a step of masking the heat-resistant film. A thermal oxidation process is performed to form a thermal oxide film on the source and drain regions of the substrate and on the sidewalls of the dirt electrode, and then anisotropic dry etching is performed to leave a thermal oxide film on the sidewalls of the gate electrode to form a thermal oxide film on the sidewalls of the gate electrode. a step of removing the thermally oxidized film and the thermal oxide film on the source and drain regions, a step of doping the source and drain regions with impurities, and then forming a metal film on the source and drain regions in a self-aligned manner. A method for manufacturing a semiconductor device, comprising the steps of: